Lines Matching refs:hw
127 static int e1000_setup_link(struct e1000_hw *hw);
128 static int e1000_setup_fiber_link(struct e1000_hw *hw);
129 static int e1000_setup_copper_link(struct e1000_hw *hw);
130 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
131 static void e1000_config_collision_dist(struct e1000_hw *hw);
132 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
133 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
134 static int e1000_check_for_link(struct e1000_hw *hw);
135 static int e1000_wait_autoneg(struct e1000_hw *hw);
136 static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
138 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
140 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
142 static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
143 static int e1000_phy_reset(struct e1000_hw *hw);
144 static int e1000_detect_gig_phy(struct e1000_hw *hw);
145 static void e1000_set_media_type(struct e1000_hw *hw);
147 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
148 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
149 static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
152 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
153 static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
162 void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd) in e1000_raise_ee_clk() argument
168 E1000_WRITE_REG(hw, EECD, *eecd); in e1000_raise_ee_clk()
169 E1000_WRITE_FLUSH(hw); in e1000_raise_ee_clk()
179 void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd) in e1000_lower_ee_clk() argument
185 E1000_WRITE_REG(hw, EECD, *eecd); in e1000_lower_ee_clk()
186 E1000_WRITE_FLUSH(hw); in e1000_lower_ee_clk()
198 e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count) in e1000_shift_out_ee_bits() argument
208 eecd = E1000_READ_REG(hw, EECD); in e1000_shift_out_ee_bits()
221 E1000_WRITE_REG(hw, EECD, eecd); in e1000_shift_out_ee_bits()
222 E1000_WRITE_FLUSH(hw); in e1000_shift_out_ee_bits()
226 e1000_raise_ee_clk(hw, &eecd); in e1000_shift_out_ee_bits()
227 e1000_lower_ee_clk(hw, &eecd); in e1000_shift_out_ee_bits()
235 E1000_WRITE_REG(hw, EECD, eecd); in e1000_shift_out_ee_bits()
244 e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count) in e1000_shift_in_ee_bits() argument
257 eecd = E1000_READ_REG(hw, EECD); in e1000_shift_in_ee_bits()
264 e1000_raise_ee_clk(hw, &eecd); in e1000_shift_in_ee_bits()
266 eecd = E1000_READ_REG(hw, EECD); in e1000_shift_in_ee_bits()
272 e1000_lower_ee_clk(hw, &eecd); in e1000_shift_in_ee_bits()
283 void e1000_standby_eeprom(struct e1000_hw *hw) in e1000_standby_eeprom() argument
285 struct e1000_eeprom_info *eeprom = &hw->eeprom; in e1000_standby_eeprom()
288 eecd = E1000_READ_REG(hw, EECD); in e1000_standby_eeprom()
292 E1000_WRITE_REG(hw, EECD, eecd); in e1000_standby_eeprom()
293 E1000_WRITE_FLUSH(hw); in e1000_standby_eeprom()
298 E1000_WRITE_REG(hw, EECD, eecd); in e1000_standby_eeprom()
299 E1000_WRITE_FLUSH(hw); in e1000_standby_eeprom()
304 E1000_WRITE_REG(hw, EECD, eecd); in e1000_standby_eeprom()
305 E1000_WRITE_FLUSH(hw); in e1000_standby_eeprom()
310 E1000_WRITE_REG(hw, EECD, eecd); in e1000_standby_eeprom()
311 E1000_WRITE_FLUSH(hw); in e1000_standby_eeprom()
316 E1000_WRITE_REG(hw, EECD, eecd); in e1000_standby_eeprom()
317 E1000_WRITE_FLUSH(hw); in e1000_standby_eeprom()
320 E1000_WRITE_REG(hw, EECD, eecd); in e1000_standby_eeprom()
321 E1000_WRITE_FLUSH(hw); in e1000_standby_eeprom()
331 static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) in e1000_is_onboard_nvm_eeprom() argument
337 if (hw->mac_type == e1000_ich8lan) in e1000_is_onboard_nvm_eeprom()
340 if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) { in e1000_is_onboard_nvm_eeprom()
341 eecd = E1000_READ_REG(hw, EECD); in e1000_is_onboard_nvm_eeprom()
361 int32_t e1000_acquire_eeprom(struct e1000_hw *hw) in e1000_acquire_eeprom() argument
363 struct e1000_eeprom_info *eeprom = &hw->eeprom; in e1000_acquire_eeprom()
368 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) in e1000_acquire_eeprom()
370 eecd = E1000_READ_REG(hw, EECD); in e1000_acquire_eeprom()
372 if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) { in e1000_acquire_eeprom()
374 if (hw->mac_type > e1000_82544) { in e1000_acquire_eeprom()
376 E1000_WRITE_REG(hw, EECD, eecd); in e1000_acquire_eeprom()
377 eecd = E1000_READ_REG(hw, EECD); in e1000_acquire_eeprom()
382 eecd = E1000_READ_REG(hw, EECD); in e1000_acquire_eeprom()
386 E1000_WRITE_REG(hw, EECD, eecd); in e1000_acquire_eeprom()
398 E1000_WRITE_REG(hw, EECD, eecd); in e1000_acquire_eeprom()
402 E1000_WRITE_REG(hw, EECD, eecd); in e1000_acquire_eeprom()
406 E1000_WRITE_REG(hw, EECD, eecd); in e1000_acquire_eeprom()
420 static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) in e1000_init_eeprom_params() argument
422 struct e1000_eeprom_info *eeprom = &hw->eeprom; in e1000_init_eeprom_params()
427 if (hw->mac_type == e1000_igb) in e1000_init_eeprom_params()
428 eecd = E1000_READ_REG(hw, I210_EECD); in e1000_init_eeprom_params()
430 eecd = E1000_READ_REG(hw, EECD); in e1000_init_eeprom_params()
434 switch (hw->mac_type) { in e1000_init_eeprom_params()
522 if (e1000_is_onboard_nvm_eeprom(hw) == false) { in e1000_init_eeprom_params()
532 E1000_WRITE_REG(hw, EECD, eecd); in e1000_init_eeprom_params()
569 if (hw->mac_type <= e1000_82547_rev_2) { in e1000_init_eeprom_params()
572 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, in e1000_init_eeprom_params()
601 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) in e1000_poll_eerd_eewr_done() argument
609 if (hw->mac_type == e1000_igb) in e1000_poll_eerd_eewr_done()
610 reg = E1000_READ_REG(hw, I210_EERD); in e1000_poll_eerd_eewr_done()
612 reg = E1000_READ_REG(hw, EERD); in e1000_poll_eerd_eewr_done()
614 if (hw->mac_type == e1000_igb) in e1000_poll_eerd_eewr_done()
615 reg = E1000_READ_REG(hw, I210_EEWR); in e1000_poll_eerd_eewr_done()
617 reg = E1000_READ_REG(hw, EEWR); in e1000_poll_eerd_eewr_done()
639 e1000_read_eeprom_eerd(struct e1000_hw *hw, in e1000_read_eeprom_eerd() argument
651 if (hw->mac_type == e1000_igb) in e1000_read_eeprom_eerd()
652 E1000_WRITE_REG(hw, I210_EERD, eerd); in e1000_read_eeprom_eerd()
654 E1000_WRITE_REG(hw, EERD, eerd); in e1000_read_eeprom_eerd()
656 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); in e1000_read_eeprom_eerd()
661 if (hw->mac_type == e1000_igb) { in e1000_read_eeprom_eerd()
662 data[i] = (E1000_READ_REG(hw, I210_EERD) >> in e1000_read_eeprom_eerd()
665 data[i] = (E1000_READ_REG(hw, EERD) >> in e1000_read_eeprom_eerd()
674 void e1000_release_eeprom(struct e1000_hw *hw) in e1000_release_eeprom() argument
680 eecd = E1000_READ_REG(hw, EECD); in e1000_release_eeprom()
682 if (hw->eeprom.type == e1000_eeprom_spi) { in e1000_release_eeprom()
686 E1000_WRITE_REG(hw, EECD, eecd); in e1000_release_eeprom()
688 udelay(hw->eeprom.delay_usec); in e1000_release_eeprom()
689 } else if (hw->eeprom.type == e1000_eeprom_microwire) { in e1000_release_eeprom()
695 E1000_WRITE_REG(hw, EECD, eecd); in e1000_release_eeprom()
699 E1000_WRITE_REG(hw, EECD, eecd); in e1000_release_eeprom()
700 E1000_WRITE_FLUSH(hw); in e1000_release_eeprom()
701 udelay(hw->eeprom.delay_usec); in e1000_release_eeprom()
705 E1000_WRITE_REG(hw, EECD, eecd); in e1000_release_eeprom()
706 E1000_WRITE_FLUSH(hw); in e1000_release_eeprom()
707 udelay(hw->eeprom.delay_usec); in e1000_release_eeprom()
711 if (hw->mac_type > e1000_82544) { in e1000_release_eeprom()
713 E1000_WRITE_REG(hw, EECD, eecd); in e1000_release_eeprom()
716 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); in e1000_release_eeprom()
725 e1000_spi_eeprom_ready(struct e1000_hw *hw) in e1000_spi_eeprom_ready() argument
739 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, in e1000_spi_eeprom_ready()
740 hw->eeprom.opcode_bits); in e1000_spi_eeprom_ready()
741 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); in e1000_spi_eeprom_ready()
748 e1000_standby_eeprom(hw); in e1000_spi_eeprom_ready()
770 e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, in e1000_read_eeprom() argument
773 struct e1000_eeprom_info *eeprom = &hw->eeprom; in e1000_read_eeprom()
780 e1000_init_eeprom_params(hw); in e1000_read_eeprom()
797 if (e1000_is_onboard_nvm_eeprom(hw) == true && in e1000_read_eeprom()
798 hw->eeprom.use_eerd == false) { in e1000_read_eeprom()
801 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) in e1000_read_eeprom()
807 return e1000_read_eeprom_eerd(hw, offset, words, data); in e1000_read_eeprom()
815 if (e1000_spi_eeprom_ready(hw)) { in e1000_read_eeprom()
816 e1000_release_eeprom(hw); in e1000_read_eeprom()
820 e1000_standby_eeprom(hw); in e1000_read_eeprom()
828 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); in e1000_read_eeprom()
829 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), in e1000_read_eeprom()
839 word_in = e1000_shift_in_ee_bits(hw, 16); in e1000_read_eeprom()
845 e1000_shift_out_ee_bits(hw, in e1000_read_eeprom()
848 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), in e1000_read_eeprom()
853 data[i] = e1000_shift_in_ee_bits(hw, 16); in e1000_read_eeprom()
854 e1000_standby_eeprom(hw); in e1000_read_eeprom()
859 e1000_release_eeprom(hw); in e1000_read_eeprom()
873 static int e1000_validate_eeprom_checksum(struct e1000_hw *hw) in e1000_validate_eeprom_checksum() argument
882 E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n"); in e1000_validate_eeprom_checksum()
887 if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) { in e1000_validate_eeprom_checksum()
888 E1000_ERR(hw, "Unable to read EEPROM!\n"); in e1000_validate_eeprom_checksum()
904 E1000_ERR(hw, "EEPROM checksum is incorrect!\n"); in e1000_validate_eeprom_checksum()
905 E1000_ERR(hw, " ...register was 0x%04hx, calculated 0x%04hx\n", in e1000_validate_eeprom_checksum()
921 e1000_set_phy_mode(struct e1000_hw *hw) in e1000_set_phy_mode() argument
929 if ((hw->mac_type == e1000_82545_rev_3) && in e1000_set_phy_mode()
930 (hw->media_type == e1000_media_type_copper)) { in e1000_set_phy_mode()
931 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, in e1000_set_phy_mode()
938 ret_val = e1000_write_phy_reg(hw, in e1000_set_phy_mode()
942 ret_val = e1000_write_phy_reg(hw, in e1000_set_phy_mode()
947 hw->phy_reset_disable = false; in e1000_set_phy_mode()
966 e1000_get_software_semaphore(struct e1000_hw *hw) in e1000_get_software_semaphore() argument
968 int32_t timeout = hw->eeprom.word_size + 1; in e1000_get_software_semaphore()
973 if (hw->mac_type != e1000_80003es2lan) in e1000_get_software_semaphore()
977 swsm = E1000_READ_REG(hw, SWSM); in e1000_get_software_semaphore()
1004 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) in e1000_put_hw_eeprom_semaphore() argument
1011 if (!hw->eeprom_semaphore_present) in e1000_put_hw_eeprom_semaphore()
1014 swsm = E1000_READ_REG(hw, SWSM); in e1000_put_hw_eeprom_semaphore()
1015 if (hw->mac_type == e1000_80003es2lan) { in e1000_put_hw_eeprom_semaphore()
1020 E1000_WRITE_REG(hw, SWSM, swsm); in e1000_put_hw_eeprom_semaphore()
1036 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) in e1000_get_hw_eeprom_semaphore() argument
1044 if (!hw->eeprom_semaphore_present) in e1000_get_hw_eeprom_semaphore()
1047 if (hw->mac_type == e1000_80003es2lan) { in e1000_get_hw_eeprom_semaphore()
1049 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) in e1000_get_hw_eeprom_semaphore()
1054 timeout = hw->eeprom.word_size + 1; in e1000_get_hw_eeprom_semaphore()
1056 swsm = E1000_READ_REG(hw, SWSM); in e1000_get_hw_eeprom_semaphore()
1058 E1000_WRITE_REG(hw, SWSM, swsm); in e1000_get_hw_eeprom_semaphore()
1060 swsm = E1000_READ_REG(hw, SWSM); in e1000_get_hw_eeprom_semaphore()
1070 e1000_put_hw_eeprom_semaphore(hw); in e1000_get_hw_eeprom_semaphore()
1081 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) in e1000_swfw_sync_acquire() argument
1090 if (e1000_get_hw_eeprom_semaphore(hw)) in e1000_swfw_sync_acquire()
1093 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); in e1000_swfw_sync_acquire()
1099 e1000_put_hw_eeprom_semaphore(hw); in e1000_swfw_sync_acquire()
1110 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); in e1000_swfw_sync_acquire()
1112 e1000_put_hw_eeprom_semaphore(hw); in e1000_swfw_sync_acquire()
1116 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) in e1000_swfw_sync_release() argument
1121 while (e1000_get_hw_eeprom_semaphore(hw)) in e1000_swfw_sync_release()
1124 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); in e1000_swfw_sync_release()
1126 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); in e1000_swfw_sync_release()
1128 e1000_put_hw_eeprom_semaphore(hw); in e1000_swfw_sync_release()
1131 static bool e1000_is_second_port(struct e1000_hw *hw) in e1000_is_second_port() argument
1133 switch (hw->mac_type) { in e1000_is_second_port()
1137 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) in e1000_is_second_port()
1153 e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6]) in e1000_read_mac_addr() argument
1164 if (hw->mac_type == e1000_igb) { in e1000_read_mac_addr()
1167 reg_data = E1000_READ_REG_ARRAY(hw, RA, 0); in e1000_read_mac_addr()
1171 reg_data = E1000_READ_REG_ARRAY(hw, RA, 1); in e1000_read_mac_addr()
1173 } else if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { in e1000_read_mac_addr()
1182 if (e1000_is_second_port(hw)) in e1000_read_mac_addr()
1199 e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6]) in e1000_init_rx_addrs() argument
1215 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); in e1000_init_rx_addrs()
1216 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); in e1000_init_rx_addrs()
1221 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); in e1000_init_rx_addrs()
1222 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); in e1000_init_rx_addrs()
1232 e1000_clear_vfta(struct e1000_hw *hw) in e1000_clear_vfta() argument
1237 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); in e1000_clear_vfta()
1246 e1000_set_mac_type(struct e1000_hw *hw) in e1000_set_mac_type() argument
1250 switch (hw->device_id) { in e1000_set_mac_type()
1252 switch (hw->revision_id) { in e1000_set_mac_type()
1254 hw->mac_type = e1000_82542_rev2_0; in e1000_set_mac_type()
1257 hw->mac_type = e1000_82542_rev2_1; in e1000_set_mac_type()
1266 hw->mac_type = e1000_82543; in e1000_set_mac_type()
1272 hw->mac_type = e1000_82544; in e1000_set_mac_type()
1279 hw->mac_type = e1000_82540; in e1000_set_mac_type()
1283 hw->mac_type = e1000_82545; in e1000_set_mac_type()
1288 hw->mac_type = e1000_82545_rev_3; in e1000_set_mac_type()
1293 hw->mac_type = e1000_82546; in e1000_set_mac_type()
1301 hw->mac_type = e1000_82546_rev_3; in e1000_set_mac_type()
1306 hw->mac_type = e1000_82541; in e1000_set_mac_type()
1312 hw->mac_type = e1000_82541_rev_2; in e1000_set_mac_type()
1316 hw->mac_type = e1000_82547; in e1000_set_mac_type()
1319 hw->mac_type = e1000_82547_rev_2; in e1000_set_mac_type()
1330 hw->mac_type = e1000_82571; in e1000_set_mac_type()
1336 hw->mac_type = e1000_82572; in e1000_set_mac_type()
1341 hw->mac_type = e1000_82573; in e1000_set_mac_type()
1344 hw->mac_type = e1000_82574; in e1000_set_mac_type()
1350 hw->mac_type = e1000_80003es2lan; in e1000_set_mac_type()
1359 hw->mac_type = e1000_ich8lan; in e1000_set_mac_type()
1369 hw->mac_type = e1000_igb; in e1000_set_mac_type()
1384 e1000_reset_hw(struct e1000_hw *hw) in e1000_reset_hw() argument
1395 if (hw->mac_type < e1000_82571) in e1000_reset_hw()
1401 if (hw->mac_type == e1000_82542_rev2_0) { in e1000_reset_hw()
1404 dm_pci_write_config16(hw->pdev, PCI_COMMAND, in e1000_reset_hw()
1405 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); in e1000_reset_hw()
1407 pci_write_config_word(hw->pdev, PCI_COMMAND, in e1000_reset_hw()
1408 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); in e1000_reset_hw()
1414 if (hw->mac_type == e1000_igb) in e1000_reset_hw()
1415 E1000_WRITE_REG(hw, I210_IAM, 0); in e1000_reset_hw()
1416 E1000_WRITE_REG(hw, IMC, 0xffffffff); in e1000_reset_hw()
1422 E1000_WRITE_REG(hw, RCTL, 0); in e1000_reset_hw()
1423 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); in e1000_reset_hw()
1424 E1000_WRITE_FLUSH(hw); in e1000_reset_hw()
1427 hw->tbi_compatibility_on = false; in e1000_reset_hw()
1440 ctrl = E1000_READ_REG(hw, CTRL); in e1000_reset_hw()
1442 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); in e1000_reset_hw()
1445 if (hw->mac_type == e1000_igb) { in e1000_reset_hw()
1447 reg = E1000_READ_REG(hw, STATUS); in e1000_reset_hw()
1450 reg = E1000_READ_REG(hw, I210_EECD); in e1000_reset_hw()
1453 } else if (hw->mac_type < e1000_82540) { in e1000_reset_hw()
1456 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); in e1000_reset_hw()
1458 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); in e1000_reset_hw()
1459 E1000_WRITE_FLUSH(hw); in e1000_reset_hw()
1466 manc = E1000_READ_REG(hw, MANC); in e1000_reset_hw()
1468 E1000_WRITE_REG(hw, MANC, manc); in e1000_reset_hw()
1473 if (hw->mac_type == e1000_igb) in e1000_reset_hw()
1474 E1000_WRITE_REG(hw, I210_IAM, 0); in e1000_reset_hw()
1475 E1000_WRITE_REG(hw, IMC, 0xffffffff); in e1000_reset_hw()
1478 E1000_READ_REG(hw, ICR); in e1000_reset_hw()
1481 if (hw->mac_type == e1000_82542_rev2_0) { in e1000_reset_hw()
1483 dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); in e1000_reset_hw()
1485 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); in e1000_reset_hw()
1488 if (hw->mac_type != e1000_igb) in e1000_reset_hw()
1489 E1000_WRITE_REG(hw, PBA, pba); in e1000_reset_hw()
1502 e1000_initialize_hardware_bits(struct e1000_hw *hw) in e1000_initialize_hardware_bits() argument
1504 if ((hw->mac_type >= e1000_82571) && in e1000_initialize_hardware_bits()
1505 (!hw->initialize_hw_bits_disable)) { in e1000_initialize_hardware_bits()
1513 reg_tarc0 = E1000_READ_REG(hw, TARC0); in e1000_initialize_hardware_bits()
1517 reg_txdctl = E1000_READ_REG(hw, TXDCTL); in e1000_initialize_hardware_bits()
1519 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); in e1000_initialize_hardware_bits()
1521 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); in e1000_initialize_hardware_bits()
1523 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); in e1000_initialize_hardware_bits()
1526 switch (hw->mac_type) { in e1000_initialize_hardware_bits()
1532 reg_tarc1 = E1000_READ_REG(hw, TARC1); in e1000_initialize_hardware_bits()
1542 reg_tctl = E1000_READ_REG(hw, TCTL); in e1000_initialize_hardware_bits()
1548 E1000_WRITE_REG(hw, TARC1, reg_tarc1); in e1000_initialize_hardware_bits()
1552 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); in e1000_initialize_hardware_bits()
1557 reg_ctrl = E1000_READ_REG(hw, CTRL); in e1000_initialize_hardware_bits()
1560 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); in e1000_initialize_hardware_bits()
1561 E1000_WRITE_REG(hw, CTRL, reg_ctrl); in e1000_initialize_hardware_bits()
1565 if ((hw->media_type == e1000_media_type_fiber) in e1000_initialize_hardware_bits()
1566 || (hw->media_type == in e1000_initialize_hardware_bits()
1572 reg_tctl = E1000_READ_REG(hw, TCTL); in e1000_initialize_hardware_bits()
1573 reg_tarc1 = E1000_READ_REG(hw, TARC1); in e1000_initialize_hardware_bits()
1579 E1000_WRITE_REG(hw, TARC1, reg_tarc1); in e1000_initialize_hardware_bits()
1583 if ((hw->revision_id < 3) || in e1000_initialize_hardware_bits()
1584 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && in e1000_initialize_hardware_bits()
1585 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) in e1000_initialize_hardware_bits()
1588 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); in e1000_initialize_hardware_bits()
1590 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); in e1000_initialize_hardware_bits()
1596 reg_tctl = E1000_READ_REG(hw, TCTL); in e1000_initialize_hardware_bits()
1597 reg_tarc1 = E1000_READ_REG(hw, TARC1); in e1000_initialize_hardware_bits()
1606 E1000_WRITE_REG(hw, TARC1, reg_tarc1); in e1000_initialize_hardware_bits()
1612 E1000_WRITE_REG(hw, TARC0, reg_tarc0); in e1000_initialize_hardware_bits()
1628 e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) in e1000_init_hw() argument
1642 if ((hw->mac_type == e1000_ich8lan) && in e1000_init_hw()
1643 ((hw->revision_id < 3) || in e1000_init_hw()
1644 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && in e1000_init_hw()
1645 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { in e1000_init_hw()
1646 reg_data = E1000_READ_REG(hw, STATUS); in e1000_init_hw()
1648 E1000_WRITE_REG(hw, STATUS, reg_data); in e1000_init_hw()
1653 e1000_set_media_type(hw); in e1000_init_hw()
1657 e1000_initialize_hardware_bits(hw); in e1000_init_hw()
1662 if (hw->mac_type != e1000_ich8lan) { in e1000_init_hw()
1663 if (hw->mac_type < e1000_82545_rev_3) in e1000_init_hw()
1664 E1000_WRITE_REG(hw, VET, 0); in e1000_init_hw()
1665 e1000_clear_vfta(hw); in e1000_init_hw()
1669 if (hw->mac_type == e1000_82542_rev2_0) { in e1000_init_hw()
1672 dm_pci_write_config16(hw->pdev, PCI_COMMAND, in e1000_init_hw()
1673 hw-> in e1000_init_hw()
1676 pci_write_config_word(hw->pdev, PCI_COMMAND, in e1000_init_hw()
1677 hw-> in e1000_init_hw()
1680 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); in e1000_init_hw()
1681 E1000_WRITE_FLUSH(hw); in e1000_init_hw()
1688 e1000_init_rx_addrs(hw, enetaddr); in e1000_init_hw()
1691 if (hw->mac_type == e1000_82542_rev2_0) { in e1000_init_hw()
1692 E1000_WRITE_REG(hw, RCTL, 0); in e1000_init_hw()
1693 E1000_WRITE_FLUSH(hw); in e1000_init_hw()
1696 dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); in e1000_init_hw()
1698 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); in e1000_init_hw()
1705 if (hw->mac_type == e1000_ich8lan) in e1000_init_hw()
1708 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); in e1000_init_hw()
1711 E1000_WRITE_FLUSH(hw); in e1000_init_hw()
1714 switch (hw->mac_type) { in e1000_init_hw()
1721 if (hw->bus_type == e1000_bus_type_pcix) { in e1000_init_hw()
1723 dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER, in e1000_init_hw()
1725 dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI, in e1000_init_hw()
1728 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, in e1000_init_hw()
1730 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, in e1000_init_hw()
1745 dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER, in e1000_init_hw()
1748 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, in e1000_init_hw()
1757 if (hw->mac_type == e1000_ich8lan) in e1000_init_hw()
1759 if (hw->mac_type == e1000_igb) in e1000_init_hw()
1763 ret_val = e1000_setup_link(hw); in e1000_init_hw()
1766 if (hw->mac_type > e1000_82544) { in e1000_init_hw()
1767 ctrl = E1000_READ_REG(hw, TXDCTL); in e1000_init_hw()
1771 E1000_WRITE_REG(hw, TXDCTL, ctrl); in e1000_init_hw()
1775 if (hw->mac_type >= e1000_82571) { in e1000_init_hw()
1776 ctrl = E1000_READ_REG(hw, RXDCTL); in e1000_init_hw()
1780 E1000_WRITE_REG(hw, RXDCTL, ctrl); in e1000_init_hw()
1783 switch (hw->mac_type) { in e1000_init_hw()
1788 reg_data = E1000_READ_REG(hw, TCTL); in e1000_init_hw()
1790 E1000_WRITE_REG(hw, TCTL, reg_data); in e1000_init_hw()
1793 reg_data = E1000_READ_REG(hw, TCTL_EXT); in e1000_init_hw()
1796 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); in e1000_init_hw()
1799 reg_data = E1000_READ_REG(hw, TIPG); in e1000_init_hw()
1802 E1000_WRITE_REG(hw, TIPG, reg_data); in e1000_init_hw()
1804 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); in e1000_init_hw()
1806 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); in e1000_init_hw()
1811 ctrl = E1000_READ_REG(hw, TXDCTL1); in e1000_init_hw()
1814 E1000_WRITE_REG(hw, TXDCTL1, ctrl); in e1000_init_hw()
1818 reg_data = E1000_READ_REG(hw, GCR); in e1000_init_hw()
1820 E1000_WRITE_REG(hw, GCR, reg_data); in e1000_init_hw()
1825 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || in e1000_init_hw()
1826 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { in e1000_init_hw()
1827 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); in e1000_init_hw()
1831 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); in e1000_init_hw()
1849 e1000_setup_link(struct e1000_hw *hw) in e1000_setup_link() argument
1861 if (e1000_check_phy_reset_block(hw)) in e1000_setup_link()
1873 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, in e1000_setup_link()
1879 if (hw->fc == e1000_fc_default) { in e1000_setup_link()
1880 switch (hw->mac_type) { in e1000_setup_link()
1885 hw->fc = e1000_fc_full; in e1000_setup_link()
1889 ret_val = e1000_read_eeprom(hw, in e1000_setup_link()
1896 hw->fc = e1000_fc_none; in e1000_setup_link()
1899 hw->fc = e1000_fc_tx_pause; in e1000_setup_link()
1902 hw->fc = e1000_fc_full; in e1000_setup_link()
1911 if (hw->mac_type == e1000_82542_rev2_0) in e1000_setup_link()
1912 hw->fc &= (~e1000_fc_tx_pause); in e1000_setup_link()
1914 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) in e1000_setup_link()
1915 hw->fc &= (~e1000_fc_rx_pause); in e1000_setup_link()
1917 hw->original_fc = hw->fc; in e1000_setup_link()
1919 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); in e1000_setup_link()
1929 if (hw->mac_type == e1000_82543) { in e1000_setup_link()
1932 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); in e1000_setup_link()
1937 ret_val = (hw->media_type == e1000_media_type_fiber) ? in e1000_setup_link()
1938 e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw); in e1000_setup_link()
1952 if (hw->mac_type != e1000_ich8lan) { in e1000_setup_link()
1953 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); in e1000_setup_link()
1954 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); in e1000_setup_link()
1955 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); in e1000_setup_link()
1958 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); in e1000_setup_link()
1966 if (!(hw->fc & e1000_fc_tx_pause)) { in e1000_setup_link()
1967 E1000_WRITE_REG(hw, FCRTL, 0); in e1000_setup_link()
1968 E1000_WRITE_REG(hw, FCRTH, 0); in e1000_setup_link()
1973 if (hw->fc_send_xon) { in e1000_setup_link()
1974 E1000_WRITE_REG(hw, FCRTL, in e1000_setup_link()
1975 (hw->fc_low_water | E1000_FCRTL_XONE)); in e1000_setup_link()
1976 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); in e1000_setup_link()
1978 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); in e1000_setup_link()
1979 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); in e1000_setup_link()
1995 e1000_setup_fiber_link(struct e1000_hw *hw) in e1000_setup_fiber_link() argument
2009 ctrl = E1000_READ_REG(hw, CTRL); in e1000_setup_fiber_link()
2010 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) in e1000_setup_fiber_link()
2015 printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal, in e1000_setup_fiber_link()
2020 e1000_config_collision_dist(hw); in e1000_setup_fiber_link()
2037 switch (hw->fc) { in e1000_setup_fiber_link()
2075 E1000_WRITE_REG(hw, TXCW, txcw); in e1000_setup_fiber_link()
2076 E1000_WRITE_REG(hw, CTRL, ctrl); in e1000_setup_fiber_link()
2077 E1000_WRITE_FLUSH(hw); in e1000_setup_fiber_link()
2079 hw->txcw = txcw; in e1000_setup_fiber_link()
2087 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { in e1000_setup_fiber_link()
2091 status = E1000_READ_REG(hw, STATUS); in e1000_setup_fiber_link()
2102 hw->autoneg_failed = 1; in e1000_setup_fiber_link()
2103 ret_val = e1000_check_for_link(hw); in e1000_setup_fiber_link()
2108 hw->autoneg_failed = 0; in e1000_setup_fiber_link()
2110 hw->autoneg_failed = 0; in e1000_setup_fiber_link()
2126 e1000_copper_link_preconfig(struct e1000_hw *hw) in e1000_copper_link_preconfig() argument
2134 ctrl = E1000_READ_REG(hw, CTRL); in e1000_copper_link_preconfig()
2139 if (hw->mac_type > e1000_82543) { in e1000_copper_link_preconfig()
2142 E1000_WRITE_REG(hw, CTRL, ctrl); in e1000_copper_link_preconfig()
2146 E1000_WRITE_REG(hw, CTRL, ctrl); in e1000_copper_link_preconfig()
2147 ret_val = e1000_phy_hw_reset(hw); in e1000_copper_link_preconfig()
2153 ret_val = e1000_detect_gig_phy(hw); in e1000_copper_link_preconfig()
2158 DEBUGOUT("Phy ID = %x\n", hw->phy_id); in e1000_copper_link_preconfig()
2161 ret_val = e1000_set_phy_mode(hw); in e1000_copper_link_preconfig()
2164 if ((hw->mac_type == e1000_82545_rev_3) || in e1000_copper_link_preconfig()
2165 (hw->mac_type == e1000_82546_rev_3)) { in e1000_copper_link_preconfig()
2166 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, in e1000_copper_link_preconfig()
2169 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, in e1000_copper_link_preconfig()
2173 if (hw->mac_type <= e1000_82543 || in e1000_copper_link_preconfig()
2174 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || in e1000_copper_link_preconfig()
2175 hw->mac_type == e1000_82541_rev_2 in e1000_copper_link_preconfig()
2176 || hw->mac_type == e1000_82547_rev_2) in e1000_copper_link_preconfig()
2177 hw->phy_reset_disable = false; in e1000_copper_link_preconfig()
2197 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) in e1000_set_d3_lplu_state() argument
2204 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 in e1000_set_d3_lplu_state()
2205 && hw->phy_type != e1000_phy_igp_3) in e1000_set_d3_lplu_state()
2211 if (hw->mac_type == e1000_82541_rev_2 in e1000_set_d3_lplu_state()
2212 || hw->mac_type == e1000_82547_rev_2) { in e1000_set_d3_lplu_state()
2213 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, in e1000_set_d3_lplu_state()
2217 } else if (hw->mac_type == e1000_ich8lan) { in e1000_set_d3_lplu_state()
2221 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); in e1000_set_d3_lplu_state()
2223 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, in e1000_set_d3_lplu_state()
2230 if (hw->mac_type == e1000_82541_rev_2 || in e1000_set_d3_lplu_state()
2231 hw->mac_type == e1000_82547_rev_2) { in e1000_set_d3_lplu_state()
2233 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, in e1000_set_d3_lplu_state()
2238 if (hw->mac_type == e1000_ich8lan) { in e1000_set_d3_lplu_state()
2240 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); in e1000_set_d3_lplu_state()
2243 ret_val = e1000_write_phy_reg(hw, in e1000_set_d3_lplu_state()
2254 if (hw->smart_speed == e1000_smart_speed_on) { in e1000_set_d3_lplu_state()
2255 ret_val = e1000_read_phy_reg(hw, in e1000_set_d3_lplu_state()
2261 ret_val = e1000_write_phy_reg(hw, in e1000_set_d3_lplu_state()
2265 } else if (hw->smart_speed == e1000_smart_speed_off) { in e1000_set_d3_lplu_state()
2266 ret_val = e1000_read_phy_reg(hw, in e1000_set_d3_lplu_state()
2272 ret_val = e1000_write_phy_reg(hw, in e1000_set_d3_lplu_state()
2278 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) in e1000_set_d3_lplu_state()
2279 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || in e1000_set_d3_lplu_state()
2280 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { in e1000_set_d3_lplu_state()
2282 if (hw->mac_type == e1000_82541_rev_2 || in e1000_set_d3_lplu_state()
2283 hw->mac_type == e1000_82547_rev_2) { in e1000_set_d3_lplu_state()
2285 ret_val = e1000_write_phy_reg(hw, in e1000_set_d3_lplu_state()
2290 if (hw->mac_type == e1000_ich8lan) { in e1000_set_d3_lplu_state()
2292 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); in e1000_set_d3_lplu_state()
2295 ret_val = e1000_write_phy_reg(hw, in e1000_set_d3_lplu_state()
2303 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, in e1000_set_d3_lplu_state()
2309 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, in e1000_set_d3_lplu_state()
2332 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) in e1000_set_d0_lplu_state() argument
2339 if (hw->mac_type <= e1000_82547_rev_2) in e1000_set_d0_lplu_state()
2342 if (hw->mac_type == e1000_ich8lan) { in e1000_set_d0_lplu_state()
2343 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); in e1000_set_d0_lplu_state()
2344 } else if (hw->mac_type == e1000_igb) { in e1000_set_d0_lplu_state()
2345 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL); in e1000_set_d0_lplu_state()
2347 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, in e1000_set_d0_lplu_state()
2354 if (hw->mac_type == e1000_ich8lan) { in e1000_set_d0_lplu_state()
2356 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); in e1000_set_d0_lplu_state()
2357 } else if (hw->mac_type == e1000_igb) { in e1000_set_d0_lplu_state()
2359 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); in e1000_set_d0_lplu_state()
2362 ret_val = e1000_write_phy_reg(hw, in e1000_set_d0_lplu_state()
2368 if (hw->mac_type == e1000_igb) in e1000_set_d0_lplu_state()
2375 if (hw->smart_speed == e1000_smart_speed_on) { in e1000_set_d0_lplu_state()
2376 ret_val = e1000_read_phy_reg(hw, in e1000_set_d0_lplu_state()
2382 ret_val = e1000_write_phy_reg(hw, in e1000_set_d0_lplu_state()
2386 } else if (hw->smart_speed == e1000_smart_speed_off) { in e1000_set_d0_lplu_state()
2387 ret_val = e1000_read_phy_reg(hw, in e1000_set_d0_lplu_state()
2393 ret_val = e1000_write_phy_reg(hw, in e1000_set_d0_lplu_state()
2402 if (hw->mac_type == e1000_ich8lan) { in e1000_set_d0_lplu_state()
2404 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); in e1000_set_d0_lplu_state()
2405 } else if (hw->mac_type == e1000_igb) { in e1000_set_d0_lplu_state()
2407 E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl); in e1000_set_d0_lplu_state()
2410 ret_val = e1000_write_phy_reg(hw, in e1000_set_d0_lplu_state()
2416 if (hw->mac_type == e1000_igb) in e1000_set_d0_lplu_state()
2420 ret_val = e1000_read_phy_reg(hw, in e1000_set_d0_lplu_state()
2426 ret_val = e1000_write_phy_reg(hw, in e1000_set_d0_lplu_state()
2441 e1000_copper_link_igp_setup(struct e1000_hw *hw) in e1000_copper_link_igp_setup() argument
2449 if (hw->phy_reset_disable) in e1000_copper_link_igp_setup()
2452 ret_val = e1000_phy_reset(hw); in e1000_copper_link_igp_setup()
2460 if (hw->mac_type != e1000_ich8lan) { in e1000_copper_link_igp_setup()
2462 led_ctrl = E1000_READ_REG(hw, LEDCTL); in e1000_copper_link_igp_setup()
2465 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); in e1000_copper_link_igp_setup()
2469 if (hw->phy_type == e1000_phy_igp) { in e1000_copper_link_igp_setup()
2471 ret_val = e1000_set_d3_lplu_state(hw, false); in e1000_copper_link_igp_setup()
2479 ret_val = e1000_set_d0_lplu_state(hw, false); in e1000_copper_link_igp_setup()
2485 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); in e1000_copper_link_igp_setup()
2489 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { in e1000_copper_link_igp_setup()
2490 hw->dsp_config_state = e1000_dsp_config_disabled; in e1000_copper_link_igp_setup()
2494 hw->mdix = 1; in e1000_copper_link_igp_setup()
2497 hw->dsp_config_state = e1000_dsp_config_enabled; in e1000_copper_link_igp_setup()
2500 switch (hw->mdix) { in e1000_copper_link_igp_setup()
2513 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); in e1000_copper_link_igp_setup()
2518 if (hw->autoneg) { in e1000_copper_link_igp_setup()
2519 e1000_ms_type phy_ms_setting = hw->master_slave; in e1000_copper_link_igp_setup()
2521 if (hw->ffe_config_state == e1000_ffe_config_active) in e1000_copper_link_igp_setup()
2522 hw->ffe_config_state = e1000_ffe_config_enabled; in e1000_copper_link_igp_setup()
2524 if (hw->dsp_config_state == e1000_dsp_config_activated) in e1000_copper_link_igp_setup()
2525 hw->dsp_config_state = e1000_dsp_config_enabled; in e1000_copper_link_igp_setup()
2530 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { in e1000_copper_link_igp_setup()
2532 ret_val = e1000_read_phy_reg(hw, in e1000_copper_link_igp_setup()
2537 ret_val = e1000_write_phy_reg(hw, in e1000_copper_link_igp_setup()
2542 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, in e1000_copper_link_igp_setup()
2547 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, in e1000_copper_link_igp_setup()
2553 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); in e1000_copper_link_igp_setup()
2558 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? in e1000_copper_link_igp_setup()
2577 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); in e1000_copper_link_igp_setup()
2591 e1000_check_mng_mode(struct e1000_hw *hw) in e1000_check_mng_mode() argument
2596 fwsm = E1000_READ_REG(hw, FWSM); in e1000_check_mng_mode()
2598 if (hw->mac_type == e1000_ich8lan) { in e1000_check_mng_mode()
2610 e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data) in e1000_write_kmrn_reg() argument
2616 if (e1000_is_second_port(hw)) in e1000_write_kmrn_reg()
2619 if (e1000_swfw_sync_acquire(hw, swfw)) in e1000_write_kmrn_reg()
2624 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); in e1000_write_kmrn_reg()
2631 e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data) in e1000_read_kmrn_reg() argument
2637 if (e1000_is_second_port(hw)) in e1000_read_kmrn_reg()
2640 if (e1000_swfw_sync_acquire(hw, swfw)) { in e1000_read_kmrn_reg()
2648 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); in e1000_read_kmrn_reg()
2652 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); in e1000_read_kmrn_reg()
2664 e1000_copper_link_ggp_setup(struct e1000_hw *hw) in e1000_copper_link_ggp_setup() argument
2672 if (!hw->phy_reset_disable) { in e1000_copper_link_ggp_setup()
2674 ret_val = e1000_read_phy_reg(hw, in e1000_copper_link_ggp_setup()
2683 ret_val = e1000_write_phy_reg(hw, in e1000_copper_link_ggp_setup()
2695 ret_val = e1000_read_phy_reg(hw, in e1000_copper_link_ggp_setup()
2702 switch (hw->mdix) { in e1000_copper_link_ggp_setup()
2722 ret_val = e1000_write_phy_reg(hw, in e1000_copper_link_ggp_setup()
2729 ret_val = e1000_phy_reset(hw); in e1000_copper_link_ggp_setup()
2736 if (hw->mac_type == e1000_80003es2lan) { in e1000_copper_link_ggp_setup()
2738 ret_val = e1000_write_kmrn_reg(hw, in e1000_copper_link_ggp_setup()
2745 ret_val = e1000_read_phy_reg(hw, in e1000_copper_link_ggp_setup()
2751 ret_val = e1000_write_phy_reg(hw, in e1000_copper_link_ggp_setup()
2757 reg_data = E1000_READ_REG(hw, CTRL_EXT); in e1000_copper_link_ggp_setup()
2759 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); in e1000_copper_link_ggp_setup()
2761 ret_val = e1000_read_phy_reg(hw, in e1000_copper_link_ggp_setup()
2770 if (e1000_check_mng_mode(hw) == false) { in e1000_copper_link_ggp_setup()
2773 ret_val = e1000_write_phy_reg(hw, in e1000_copper_link_ggp_setup()
2778 ret_val = e1000_read_phy_reg(hw, in e1000_copper_link_ggp_setup()
2784 ret_val = e1000_write_phy_reg(hw, in e1000_copper_link_ggp_setup()
2794 ret_val = e1000_read_phy_reg(hw, in e1000_copper_link_ggp_setup()
2799 ret_val = e1000_write_phy_reg(hw, in e1000_copper_link_ggp_setup()
2813 e1000_copper_link_mgp_setup(struct e1000_hw *hw) in e1000_copper_link_mgp_setup() argument
2820 if (hw->phy_reset_disable) in e1000_copper_link_mgp_setup()
2824 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); in e1000_copper_link_mgp_setup()
2839 switch (hw->mdix) { in e1000_copper_link_mgp_setup()
2862 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); in e1000_copper_link_mgp_setup()
2866 if (hw->phy_revision < M88E1011_I_REV_4) { in e1000_copper_link_mgp_setup()
2870 ret_val = e1000_read_phy_reg(hw, in e1000_copper_link_mgp_setup()
2877 if ((hw->phy_revision == E1000_REVISION_2) && in e1000_copper_link_mgp_setup()
2878 (hw->phy_id == M88E1111_I_PHY_ID)) { in e1000_copper_link_mgp_setup()
2882 ret_val = e1000_write_phy_reg(hw, in e1000_copper_link_mgp_setup()
2892 ret_val = e1000_write_phy_reg(hw, in e1000_copper_link_mgp_setup()
2900 ret_val = e1000_phy_reset(hw); in e1000_copper_link_mgp_setup()
2916 e1000_copper_link_autoneg(struct e1000_hw *hw) in e1000_copper_link_autoneg() argument
2926 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_copper_link_autoneg()
2931 if (hw->autoneg_advertised == 0) in e1000_copper_link_autoneg()
2932 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_copper_link_autoneg()
2935 if (hw->phy_type == e1000_phy_ife) in e1000_copper_link_autoneg()
2936 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; in e1000_copper_link_autoneg()
2939 ret_val = e1000_phy_setup_autoneg(hw); in e1000_copper_link_autoneg()
2949 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); in e1000_copper_link_autoneg()
2954 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); in e1000_copper_link_autoneg()
2965 if (hw->wait_autoneg_complete) { in e1000_copper_link_autoneg()
2966 ret_val = e1000_wait_autoneg(hw); in e1000_copper_link_autoneg()
2974 hw->get_link_status = true; in e1000_copper_link_autoneg()
2992 e1000_copper_link_postconfig(struct e1000_hw *hw) in e1000_copper_link_postconfig() argument
2997 if (hw->mac_type >= e1000_82544) { in e1000_copper_link_postconfig()
2998 e1000_config_collision_dist(hw); in e1000_copper_link_postconfig()
3000 ret_val = e1000_config_mac_to_phy(hw); in e1000_copper_link_postconfig()
3006 ret_val = e1000_config_fc_after_link_up(hw); in e1000_copper_link_postconfig()
3020 e1000_setup_copper_link(struct e1000_hw *hw) in e1000_setup_copper_link() argument
3029 switch (hw->mac_type) { in e1000_setup_copper_link()
3035 ret_val = e1000_write_kmrn_reg(hw, in e1000_setup_copper_link()
3039 ret_val = e1000_read_kmrn_reg(hw, in e1000_setup_copper_link()
3044 ret_val = e1000_write_kmrn_reg(hw, in e1000_setup_copper_link()
3053 ret_val = e1000_copper_link_preconfig(hw); in e1000_setup_copper_link()
3056 switch (hw->mac_type) { in e1000_setup_copper_link()
3062 ret_val = e1000_write_kmrn_reg(hw, in e1000_setup_copper_link()
3071 if (hw->phy_type == e1000_phy_igp || in e1000_setup_copper_link()
3072 hw->phy_type == e1000_phy_igp_3 || in e1000_setup_copper_link()
3073 hw->phy_type == e1000_phy_igp_2) { in e1000_setup_copper_link()
3074 ret_val = e1000_copper_link_igp_setup(hw); in e1000_setup_copper_link()
3077 } else if (hw->phy_type == e1000_phy_m88 || in e1000_setup_copper_link()
3078 hw->phy_type == e1000_phy_igb) { in e1000_setup_copper_link()
3079 ret_val = e1000_copper_link_mgp_setup(hw); in e1000_setup_copper_link()
3082 } else if (hw->phy_type == e1000_phy_gg82563) { in e1000_setup_copper_link()
3083 ret_val = e1000_copper_link_ggp_setup(hw); in e1000_setup_copper_link()
3091 ret_val = e1000_copper_link_autoneg(hw); in e1000_setup_copper_link()
3099 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); in e1000_setup_copper_link()
3102 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); in e1000_setup_copper_link()
3108 ret_val = e1000_copper_link_postconfig(hw); in e1000_setup_copper_link()
3128 e1000_phy_setup_autoneg(struct e1000_hw *hw) in e1000_phy_setup_autoneg() argument
3137 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); in e1000_phy_setup_autoneg()
3141 if (hw->phy_type != e1000_phy_ife) { in e1000_phy_setup_autoneg()
3143 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, in e1000_phy_setup_autoneg()
3164 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised); in e1000_phy_setup_autoneg()
3167 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { in e1000_phy_setup_autoneg()
3173 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { in e1000_phy_setup_autoneg()
3179 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { in e1000_phy_setup_autoneg()
3185 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { in e1000_phy_setup_autoneg()
3191 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { in e1000_phy_setup_autoneg()
3197 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { in e1000_phy_setup_autoneg()
3218 switch (hw->fc) { in e1000_phy_setup_autoneg()
3255 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); in e1000_phy_setup_autoneg()
3261 if (hw->phy_type != e1000_phy_ife) { in e1000_phy_setup_autoneg()
3262 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, in e1000_phy_setup_autoneg()
3280 e1000_config_collision_dist(struct e1000_hw *hw) in e1000_config_collision_dist() argument
3286 if (hw->mac_type < e1000_82543) in e1000_config_collision_dist()
3291 tctl = E1000_READ_REG(hw, TCTL); in e1000_config_collision_dist()
3296 E1000_WRITE_REG(hw, TCTL, tctl); in e1000_config_collision_dist()
3297 E1000_WRITE_FLUSH(hw); in e1000_config_collision_dist()
3310 e1000_config_mac_to_phy(struct e1000_hw *hw) in e1000_config_mac_to_phy() argument
3320 ctrl = E1000_READ_REG(hw, CTRL); in e1000_config_mac_to_phy()
3328 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) { in e1000_config_mac_to_phy()
3337 e1000_config_collision_dist(hw); in e1000_config_mac_to_phy()
3347 E1000_WRITE_REG(hw, CTRL, ctrl); in e1000_config_mac_to_phy()
3363 e1000_force_mac_fc(struct e1000_hw *hw) in e1000_force_mac_fc() argument
3370 ctrl = E1000_READ_REG(hw, CTRL); in e1000_force_mac_fc()
3390 switch (hw->fc) { in e1000_force_mac_fc()
3411 if (hw->mac_type == e1000_82542_rev2_0) in e1000_force_mac_fc()
3414 E1000_WRITE_REG(hw, CTRL, ctrl); in e1000_force_mac_fc()
3430 e1000_config_fc_after_link_up(struct e1000_hw *hw) in e1000_config_fc_after_link_up() argument
3445 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) in e1000_config_fc_after_link_up()
3446 || ((hw->media_type == e1000_media_type_internal_serdes) in e1000_config_fc_after_link_up()
3447 && (hw->autoneg_failed)) in e1000_config_fc_after_link_up()
3448 || ((hw->media_type == e1000_media_type_copper) in e1000_config_fc_after_link_up()
3449 && (!hw->autoneg))) { in e1000_config_fc_after_link_up()
3450 ret_val = e1000_force_mac_fc(hw); in e1000_config_fc_after_link_up()
3462 if (hw->media_type == e1000_media_type_copper) { in e1000_config_fc_after_link_up()
3467 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { in e1000_config_fc_after_link_up()
3471 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) { in e1000_config_fc_after_link_up()
3484 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) { in e1000_config_fc_after_link_up()
3489 (hw, PHY_LP_ABILITY, in e1000_config_fc_after_link_up()
3537 if (hw->original_fc == e1000_fc_full) { in e1000_config_fc_after_link_up()
3538 hw->fc = e1000_fc_full; in e1000_config_fc_after_link_up()
3541 hw->fc = e1000_fc_rx_pause; in e1000_config_fc_after_link_up()
3559 hw->fc = e1000_fc_tx_pause; in e1000_config_fc_after_link_up()
3576 hw->fc = e1000_fc_rx_pause; in e1000_config_fc_after_link_up()
3600 else if (hw->original_fc == e1000_fc_none || in e1000_config_fc_after_link_up()
3601 hw->original_fc == e1000_fc_tx_pause) { in e1000_config_fc_after_link_up()
3602 hw->fc = e1000_fc_none; in e1000_config_fc_after_link_up()
3605 hw->fc = e1000_fc_rx_pause; in e1000_config_fc_after_link_up()
3614 e1000_get_speed_and_duplex(hw, &speed, &duplex); in e1000_config_fc_after_link_up()
3617 hw->fc = e1000_fc_none; in e1000_config_fc_after_link_up()
3622 ret_val = e1000_force_mac_fc(hw); in e1000_config_fc_after_link_up()
3644 e1000_check_for_link(struct e1000_hw *hw) in e1000_check_for_link() argument
3661 ctrl = E1000_READ_REG(hw, CTRL); in e1000_check_for_link()
3662 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) in e1000_check_for_link()
3667 status = E1000_READ_REG(hw, STATUS); in e1000_check_for_link()
3668 rxcw = E1000_READ_REG(hw, RXCW); in e1000_check_for_link()
3677 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { in e1000_check_for_link()
3683 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { in e1000_check_for_link()
3687 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { in e1000_check_for_link()
3693 hw->get_link_status = false; in e1000_check_for_link()
3707 if (hw->mac_type >= e1000_82544) in e1000_check_for_link()
3708 e1000_config_collision_dist(hw); in e1000_check_for_link()
3710 ret_val = e1000_config_mac_to_phy(hw); in e1000_check_for_link()
3722 ret_val = e1000_config_fc_after_link_up(hw); in e1000_check_for_link()
3737 if (hw->tbi_compatibility_en) { in e1000_check_for_link()
3739 (hw, PHY_LP_ABILITY, &lp_capability) < 0) { in e1000_check_for_link()
3751 if (hw->tbi_compatibility_on) { in e1000_check_for_link()
3753 rctl = E1000_READ_REG(hw, RCTL); in e1000_check_for_link()
3755 E1000_WRITE_REG(hw, RCTL, rctl); in e1000_check_for_link()
3756 hw->tbi_compatibility_on = false; in e1000_check_for_link()
3764 if (!hw->tbi_compatibility_on) { in e1000_check_for_link()
3765 hw->tbi_compatibility_on = true; in e1000_check_for_link()
3766 rctl = E1000_READ_REG(hw, RCTL); in e1000_check_for_link()
3768 E1000_WRITE_REG(hw, RCTL, rctl); in e1000_check_for_link()
3780 else if ((hw->media_type == e1000_media_type_fiber) && in e1000_check_for_link()
3784 if (hw->autoneg_failed == 0) { in e1000_check_for_link()
3785 hw->autoneg_failed = 1; in e1000_check_for_link()
3791 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); in e1000_check_for_link()
3794 ctrl = E1000_READ_REG(hw, CTRL); in e1000_check_for_link()
3796 E1000_WRITE_REG(hw, CTRL, ctrl); in e1000_check_for_link()
3799 ret_val = e1000_config_fc_after_link_up(hw); in e1000_check_for_link()
3810 else if ((hw->media_type == e1000_media_type_fiber) && in e1000_check_for_link()
3814 E1000_WRITE_REG(hw, TXCW, hw->txcw); in e1000_check_for_link()
3815 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); in e1000_check_for_link()
3826 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) in e1000_configure_kmrn_for_10_100() argument
3835 ret_val = e1000_write_kmrn_reg(hw, in e1000_configure_kmrn_for_10_100()
3841 tipg = E1000_READ_REG(hw, TIPG); in e1000_configure_kmrn_for_10_100()
3844 E1000_WRITE_REG(hw, TIPG, tipg); in e1000_configure_kmrn_for_10_100()
3846 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); in e1000_configure_kmrn_for_10_100()
3856 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); in e1000_configure_kmrn_for_10_100()
3862 e1000_configure_kmrn_for_1000(struct e1000_hw *hw) in e1000_configure_kmrn_for_1000() argument
3871 ret_val = e1000_write_kmrn_reg(hw, in e1000_configure_kmrn_for_1000()
3877 tipg = E1000_READ_REG(hw, TIPG); in e1000_configure_kmrn_for_1000()
3880 E1000_WRITE_REG(hw, TIPG, tipg); in e1000_configure_kmrn_for_1000()
3882 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); in e1000_configure_kmrn_for_1000()
3888 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); in e1000_configure_kmrn_for_1000()
3901 e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, in e1000_get_speed_and_duplex() argument
3910 if (hw->mac_type >= e1000_82543) { in e1000_get_speed_and_duplex()
3911 status = E1000_READ_REG(hw, STATUS); in e1000_get_speed_and_duplex()
3940 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { in e1000_get_speed_and_duplex()
3941 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); in e1000_get_speed_and_duplex()
3948 ret_val = e1000_read_phy_reg(hw, in e1000_get_speed_and_duplex()
3960 if ((hw->mac_type == e1000_80003es2lan) && in e1000_get_speed_and_duplex()
3961 (hw->media_type == e1000_media_type_copper)) { in e1000_get_speed_and_duplex()
3963 ret_val = e1000_configure_kmrn_for_1000(hw); in e1000_get_speed_and_duplex()
3965 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); in e1000_get_speed_and_duplex()
3978 e1000_wait_autoneg(struct e1000_hw *hw) in e1000_wait_autoneg() argument
3991 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { in e1000_wait_autoneg()
3995 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) { in e1000_wait_autoneg()
4016 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) in e1000_raise_mdi_clk() argument
4021 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); in e1000_raise_mdi_clk()
4022 E1000_WRITE_FLUSH(hw); in e1000_raise_mdi_clk()
4033 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) in e1000_lower_mdi_clk() argument
4038 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); in e1000_lower_mdi_clk()
4039 E1000_WRITE_FLUSH(hw); in e1000_lower_mdi_clk()
4053 e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) in e1000_shift_out_mdi_bits() argument
4065 ctrl = E1000_READ_REG(hw, CTRL); in e1000_shift_out_mdi_bits()
4081 E1000_WRITE_REG(hw, CTRL, ctrl); in e1000_shift_out_mdi_bits()
4082 E1000_WRITE_FLUSH(hw); in e1000_shift_out_mdi_bits()
4086 e1000_raise_mdi_clk(hw, &ctrl); in e1000_shift_out_mdi_bits()
4087 e1000_lower_mdi_clk(hw, &ctrl); in e1000_shift_out_mdi_bits()
4101 e1000_shift_in_mdi_bits(struct e1000_hw *hw) in e1000_shift_in_mdi_bits() argument
4114 ctrl = E1000_READ_REG(hw, CTRL); in e1000_shift_in_mdi_bits()
4120 E1000_WRITE_REG(hw, CTRL, ctrl); in e1000_shift_in_mdi_bits()
4121 E1000_WRITE_FLUSH(hw); in e1000_shift_in_mdi_bits()
4127 e1000_raise_mdi_clk(hw, &ctrl); in e1000_shift_in_mdi_bits()
4128 e1000_lower_mdi_clk(hw, &ctrl); in e1000_shift_in_mdi_bits()
4132 e1000_raise_mdi_clk(hw, &ctrl); in e1000_shift_in_mdi_bits()
4133 ctrl = E1000_READ_REG(hw, CTRL); in e1000_shift_in_mdi_bits()
4137 e1000_lower_mdi_clk(hw, &ctrl); in e1000_shift_in_mdi_bits()
4140 e1000_raise_mdi_clk(hw, &ctrl); in e1000_shift_in_mdi_bits()
4141 e1000_lower_mdi_clk(hw, &ctrl); in e1000_shift_in_mdi_bits()
4153 e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data) in e1000_read_phy_reg() argument
4164 if (hw->mac_type > e1000_82543) { in e1000_read_phy_reg()
4173 E1000_WRITE_REG(hw, MDIC, mdic); in e1000_read_phy_reg()
4178 mdic = E1000_READ_REG(hw, MDIC); in e1000_read_phy_reg()
4196 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); in e1000_read_phy_reg()
4212 e1000_shift_out_mdi_bits(hw, mdic, 14); in e1000_read_phy_reg()
4218 *phy_data = e1000_shift_in_mdi_bits(hw); in e1000_read_phy_reg()
4231 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) in e1000_write_phy_reg() argument
4242 if (hw->mac_type > e1000_82543) { in e1000_write_phy_reg()
4252 E1000_WRITE_REG(hw, MDIC, mdic); in e1000_write_phy_reg()
4257 mdic = E1000_READ_REG(hw, MDIC); in e1000_write_phy_reg()
4271 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); in e1000_write_phy_reg()
4284 e1000_shift_out_mdi_bits(hw, mdic, 32); in e1000_write_phy_reg()
4301 e1000_check_phy_reset_block(struct e1000_hw *hw) in e1000_check_phy_reset_block() argument
4306 if (hw->mac_type == e1000_ich8lan) { in e1000_check_phy_reset_block()
4307 fwsm = E1000_READ_REG(hw, FWSM); in e1000_check_phy_reset_block()
4312 if (hw->mac_type > e1000_82547_rev_2) in e1000_check_phy_reset_block()
4313 manc = E1000_READ_REG(hw, MANC); in e1000_check_phy_reset_block()
4328 e1000_get_phy_cfg_done(struct e1000_hw *hw) in e1000_get_phy_cfg_done() argument
4335 switch (hw->mac_type) { in e1000_get_phy_cfg_done()
4342 if (e1000_is_second_port(hw)) in e1000_get_phy_cfg_done()
4350 if (hw->mac_type == e1000_igb) { in e1000_get_phy_cfg_done()
4351 if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask) in e1000_get_phy_cfg_done()
4354 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) in e1000_get_phy_cfg_done()
4377 e1000_phy_hw_reset(struct e1000_hw *hw) in e1000_phy_hw_reset() argument
4388 ret_val = e1000_check_phy_reset_block(hw); in e1000_phy_hw_reset()
4394 if (hw->mac_type > e1000_82543) { in e1000_phy_hw_reset()
4395 if (e1000_is_second_port(hw)) in e1000_phy_hw_reset()
4398 if (e1000_swfw_sync_acquire(hw, swfw)) { in e1000_phy_hw_reset()
4406 ctrl = E1000_READ_REG(hw, CTRL); in e1000_phy_hw_reset()
4407 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); in e1000_phy_hw_reset()
4408 E1000_WRITE_FLUSH(hw); in e1000_phy_hw_reset()
4410 if (hw->mac_type < e1000_82571) in e1000_phy_hw_reset()
4415 E1000_WRITE_REG(hw, CTRL, ctrl); in e1000_phy_hw_reset()
4416 E1000_WRITE_FLUSH(hw); in e1000_phy_hw_reset()
4418 if (hw->mac_type >= e1000_82571) in e1000_phy_hw_reset()
4425 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); in e1000_phy_hw_reset()
4428 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); in e1000_phy_hw_reset()
4429 E1000_WRITE_FLUSH(hw); in e1000_phy_hw_reset()
4432 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); in e1000_phy_hw_reset()
4433 E1000_WRITE_FLUSH(hw); in e1000_phy_hw_reset()
4437 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { in e1000_phy_hw_reset()
4439 led_ctrl = E1000_READ_REG(hw, LEDCTL); in e1000_phy_hw_reset()
4442 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); in e1000_phy_hw_reset()
4445 e1000_swfw_sync_release(hw, swfw); in e1000_phy_hw_reset()
4448 ret_val = e1000_get_phy_cfg_done(hw); in e1000_phy_hw_reset()
4461 e1000_phy_init_script(struct e1000_hw *hw) in e1000_phy_init_script() argument
4467 if (hw->phy_init_script) { in e1000_phy_init_script()
4472 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); in e1000_phy_init_script()
4475 e1000_write_phy_reg(hw, 0x2F5B, 0x0003); in e1000_phy_init_script()
4479 e1000_write_phy_reg(hw, 0x0000, 0x0140); in e1000_phy_init_script()
4483 switch (hw->mac_type) { in e1000_phy_init_script()
4486 e1000_write_phy_reg(hw, 0x1F95, 0x0001); in e1000_phy_init_script()
4488 e1000_write_phy_reg(hw, 0x1F71, 0xBD21); in e1000_phy_init_script()
4490 e1000_write_phy_reg(hw, 0x1F79, 0x0018); in e1000_phy_init_script()
4492 e1000_write_phy_reg(hw, 0x1F30, 0x1600); in e1000_phy_init_script()
4494 e1000_write_phy_reg(hw, 0x1F31, 0x0014); in e1000_phy_init_script()
4496 e1000_write_phy_reg(hw, 0x1F32, 0x161C); in e1000_phy_init_script()
4498 e1000_write_phy_reg(hw, 0x1F94, 0x0003); in e1000_phy_init_script()
4500 e1000_write_phy_reg(hw, 0x1F96, 0x003F); in e1000_phy_init_script()
4502 e1000_write_phy_reg(hw, 0x2010, 0x0008); in e1000_phy_init_script()
4507 e1000_write_phy_reg(hw, 0x1F73, 0x0099); in e1000_phy_init_script()
4513 e1000_write_phy_reg(hw, 0x0000, 0x3300); in e1000_phy_init_script()
4519 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); in e1000_phy_init_script()
4521 if (hw->mac_type == e1000_82547) { in e1000_phy_init_script()
4525 e1000_read_phy_reg(hw, in e1000_phy_init_script()
4529 e1000_read_phy_reg(hw, in e1000_phy_init_script()
4552 e1000_write_phy_reg(hw, in e1000_phy_init_script()
4554 e1000_write_phy_reg(hw, in e1000_phy_init_script()
4570 e1000_phy_reset(struct e1000_hw *hw) in e1000_phy_reset() argument
4579 ret_val = e1000_check_phy_reset_block(hw); in e1000_phy_reset()
4583 switch (hw->phy_type) { in e1000_phy_reset()
4589 ret_val = e1000_phy_hw_reset(hw); in e1000_phy_reset()
4594 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); in e1000_phy_reset()
4599 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); in e1000_phy_reset()
4607 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) in e1000_phy_reset()
4608 e1000_phy_init_script(hw); in e1000_phy_reset()
4613 static int e1000_set_phy_type (struct e1000_hw *hw) in e1000_set_phy_type() argument
4617 if (hw->mac_type == e1000_undefined) in e1000_set_phy_type()
4620 switch (hw->phy_id) { in e1000_set_phy_type()
4625 hw->phy_type = e1000_phy_m88; in e1000_set_phy_type()
4628 if (hw->mac_type == e1000_82541 || in e1000_set_phy_type()
4629 hw->mac_type == e1000_82541_rev_2 || in e1000_set_phy_type()
4630 hw->mac_type == e1000_82547 || in e1000_set_phy_type()
4631 hw->mac_type == e1000_82547_rev_2) { in e1000_set_phy_type()
4632 hw->phy_type = e1000_phy_igp; in e1000_set_phy_type()
4636 hw->phy_type = e1000_phy_igp_3; in e1000_set_phy_type()
4641 hw->phy_type = e1000_phy_ife; in e1000_set_phy_type()
4644 if (hw->mac_type == e1000_80003es2lan) { in e1000_set_phy_type()
4645 hw->phy_type = e1000_phy_gg82563; in e1000_set_phy_type()
4649 hw->phy_type = e1000_phy_bm; in e1000_set_phy_type()
4652 hw->phy_type = e1000_phy_igb; in e1000_set_phy_type()
4657 hw->phy_type = e1000_phy_undefined; in e1000_set_phy_type()
4670 e1000_detect_gig_phy(struct e1000_hw *hw) in e1000_detect_gig_phy() argument
4681 if (hw->mac_type == e1000_82571 || in e1000_detect_gig_phy()
4682 hw->mac_type == e1000_82572) { in e1000_detect_gig_phy()
4683 hw->phy_id = IGP01E1000_I_PHY_ID; in e1000_detect_gig_phy()
4684 hw->phy_type = e1000_phy_igp_2; in e1000_detect_gig_phy()
4694 if (hw->mac_type == e1000_80003es2lan) in e1000_detect_gig_phy()
4695 hw->phy_type = e1000_phy_gg82563; in e1000_detect_gig_phy()
4698 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); in e1000_detect_gig_phy()
4702 hw->phy_id = (uint32_t) (phy_id_high << 16); in e1000_detect_gig_phy()
4704 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); in e1000_detect_gig_phy()
4708 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); in e1000_detect_gig_phy()
4709 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; in e1000_detect_gig_phy()
4711 switch (hw->mac_type) { in e1000_detect_gig_phy()
4713 if (hw->phy_id == M88E1000_E_PHY_ID) in e1000_detect_gig_phy()
4717 if (hw->phy_id == M88E1000_I_PHY_ID) in e1000_detect_gig_phy()
4725 if (hw->phy_id == M88E1011_I_PHY_ID) in e1000_detect_gig_phy()
4732 if(hw->phy_id == IGP01E1000_I_PHY_ID) in e1000_detect_gig_phy()
4737 if (hw->phy_id == M88E1111_I_PHY_ID) in e1000_detect_gig_phy()
4741 if (hw->phy_id == BME1000_E_PHY_ID) in e1000_detect_gig_phy()
4745 if (hw->phy_id == GG82563_E_PHY_ID) in e1000_detect_gig_phy()
4749 if (hw->phy_id == IGP03E1000_E_PHY_ID) in e1000_detect_gig_phy()
4751 if (hw->phy_id == IFE_E_PHY_ID) in e1000_detect_gig_phy()
4753 if (hw->phy_id == IFE_PLUS_E_PHY_ID) in e1000_detect_gig_phy()
4755 if (hw->phy_id == IFE_C_E_PHY_ID) in e1000_detect_gig_phy()
4759 if (hw->phy_id == I210_I_PHY_ID) in e1000_detect_gig_phy()
4763 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); in e1000_detect_gig_phy()
4767 phy_init_status = e1000_set_phy_type(hw); in e1000_detect_gig_phy()
4770 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); in e1000_detect_gig_phy()
4773 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id); in e1000_detect_gig_phy()
4783 e1000_set_media_type(struct e1000_hw *hw) in e1000_set_media_type() argument
4789 if (hw->mac_type != e1000_82543) { in e1000_set_media_type()
4791 hw->tbi_compatibility_en = false; in e1000_set_media_type()
4794 switch (hw->device_id) { in e1000_set_media_type()
4802 hw->media_type = e1000_media_type_internal_serdes; in e1000_set_media_type()
4805 switch (hw->mac_type) { in e1000_set_media_type()
4808 hw->media_type = e1000_media_type_fiber; in e1000_set_media_type()
4817 hw->media_type = e1000_media_type_copper; in e1000_set_media_type()
4820 status = E1000_READ_REG(hw, STATUS); in e1000_set_media_type()
4822 hw->media_type = e1000_media_type_fiber; in e1000_set_media_type()
4824 hw->tbi_compatibility_en = false; in e1000_set_media_type()
4826 hw->media_type = e1000_media_type_copper; in e1000_set_media_type()
4842 e1000_sw_init(struct e1000_hw *hw) in e1000_sw_init() argument
4848 dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); in e1000_sw_init()
4849 dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id); in e1000_sw_init()
4850 dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, in e1000_sw_init()
4851 &hw->subsystem_vendor_id); in e1000_sw_init()
4852 dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); in e1000_sw_init()
4854 dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id); in e1000_sw_init()
4855 dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); in e1000_sw_init()
4857 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); in e1000_sw_init()
4858 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); in e1000_sw_init()
4859 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, in e1000_sw_init()
4860 &hw->subsystem_vendor_id); in e1000_sw_init()
4861 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); in e1000_sw_init()
4863 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); in e1000_sw_init()
4864 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); in e1000_sw_init()
4868 result = e1000_set_mac_type(hw); in e1000_sw_init()
4870 E1000_ERR(hw, "Unknown MAC Type\n"); in e1000_sw_init()
4874 switch (hw->mac_type) { in e1000_sw_init()
4881 hw->phy_init_script = 1; in e1000_sw_init()
4886 hw->fc_high_water = E1000_FC_HIGH_THRESH; in e1000_sw_init()
4887 hw->fc_low_water = E1000_FC_LOW_THRESH; in e1000_sw_init()
4888 hw->fc_pause_time = E1000_FC_PAUSE_TIME; in e1000_sw_init()
4889 hw->fc_send_xon = 1; in e1000_sw_init()
4892 hw->tbi_compatibility_en = true; in e1000_sw_init()
4893 e1000_set_media_type(hw); in e1000_sw_init()
4895 if (hw->mac_type >= e1000_82543) { in e1000_sw_init()
4896 uint32_t status = E1000_READ_REG(hw, STATUS); in e1000_sw_init()
4900 hw->media_type = e1000_media_type_fiber; in e1000_sw_init()
4903 hw->media_type = e1000_media_type_copper; in e1000_sw_init()
4906 hw->media_type = e1000_media_type_fiber; in e1000_sw_init()
4909 hw->wait_autoneg_complete = true; in e1000_sw_init()
4910 if (hw->mac_type < e1000_82543) in e1000_sw_init()
4911 hw->report_tx_early = 0; in e1000_sw_init()
4913 hw->report_tx_early = 1; in e1000_sw_init()
4919 fill_rx(struct e1000_hw *hw) in fill_rx() argument
4942 E1000_WRITE_REG(hw, RDT, rx_tail); in fill_rx()
4953 e1000_configure_tx(struct e1000_hw *hw) in e1000_configure_tx() argument
4959 E1000_WRITE_REG(hw, TDBAL, lower_32_bits((unsigned long)tx_base)); in e1000_configure_tx()
4960 E1000_WRITE_REG(hw, TDBAH, upper_32_bits((unsigned long)tx_base)); in e1000_configure_tx()
4962 E1000_WRITE_REG(hw, TDLEN, 128); in e1000_configure_tx()
4965 E1000_WRITE_REG(hw, TDH, 0); in e1000_configure_tx()
4966 E1000_WRITE_REG(hw, TDT, 0); in e1000_configure_tx()
4970 if (hw->mac_type <= e1000_82547_rev_2 && in e1000_configure_tx()
4971 (hw->media_type == e1000_media_type_fiber || in e1000_configure_tx()
4972 hw->media_type == e1000_media_type_internal_serdes)) in e1000_configure_tx()
4978 switch (hw->mac_type) { in e1000_configure_tx()
4996 E1000_WRITE_REG(hw, TIPG, tipg); in e1000_configure_tx()
4998 tctl = E1000_READ_REG(hw, TCTL); in e1000_configure_tx()
5003 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) { in e1000_configure_tx()
5004 tarc = E1000_READ_REG(hw, TARC0); in e1000_configure_tx()
5008 } else if (hw->mac_type == e1000_80003es2lan) { in e1000_configure_tx()
5009 tarc = E1000_READ_REG(hw, TARC0); in e1000_configure_tx()
5011 E1000_WRITE_REG(hw, TARC0, tarc); in e1000_configure_tx()
5012 tarc = E1000_READ_REG(hw, TARC1); in e1000_configure_tx()
5014 E1000_WRITE_REG(hw, TARC1, tarc); in e1000_configure_tx()
5018 e1000_config_collision_dist(hw); in e1000_configure_tx()
5020 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; in e1000_configure_tx()
5023 if (hw->mac_type < e1000_82543) in e1000_configure_tx()
5024 hw->txd_cmd |= E1000_TXD_CMD_RPS; in e1000_configure_tx()
5026 hw->txd_cmd |= E1000_TXD_CMD_RS; in e1000_configure_tx()
5029 if (hw->mac_type == e1000_igb) { in e1000_configure_tx()
5030 E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10); in e1000_configure_tx()
5032 uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL); in e1000_configure_tx()
5034 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); in e1000_configure_tx()
5040 E1000_WRITE_REG(hw, TCTL, tctl); in e1000_configure_tx()
5050 e1000_setup_rctl(struct e1000_hw *hw) in e1000_setup_rctl() argument
5054 rctl = E1000_READ_REG(hw, RCTL); in e1000_setup_rctl()
5062 if (hw->tbi_compatibility_on == 1) in e1000_setup_rctl()
5070 E1000_WRITE_REG(hw, RCTL, rctl); in e1000_setup_rctl()
5080 e1000_configure_rx(struct e1000_hw *hw) in e1000_configure_rx() argument
5086 rctl = E1000_READ_REG(hw, RCTL); in e1000_configure_rx()
5087 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN); in e1000_configure_rx()
5088 if (hw->mac_type >= e1000_82540) { in e1000_configure_rx()
5093 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR); in e1000_configure_rx()
5096 if (hw->mac_type >= e1000_82571) { in e1000_configure_rx()
5097 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); in e1000_configure_rx()
5100 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); in e1000_configure_rx()
5101 E1000_WRITE_FLUSH(hw); in e1000_configure_rx()
5104 E1000_WRITE_REG(hw, RDBAL, lower_32_bits((unsigned long)rx_base)); in e1000_configure_rx()
5105 E1000_WRITE_REG(hw, RDBAH, upper_32_bits((unsigned long)rx_base)); in e1000_configure_rx()
5107 E1000_WRITE_REG(hw, RDLEN, 128); in e1000_configure_rx()
5110 E1000_WRITE_REG(hw, RDH, 0); in e1000_configure_rx()
5111 E1000_WRITE_REG(hw, RDT, 0); in e1000_configure_rx()
5114 if (hw->mac_type == e1000_igb) { in e1000_configure_rx()
5116 uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL); in e1000_configure_rx()
5118 E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl); in e1000_configure_rx()
5122 E1000_WRITE_REG(hw, RCTL, rctl); in e1000_configure_rx()
5124 fill_rx(hw); in e1000_configure_rx()
5131 _e1000_poll(struct e1000_hw *hw) in _e1000_poll() argument
5156 static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length) in _e1000_transmit() argument
5166 txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet)); in _e1000_transmit()
5167 txp->lower.data = cpu_to_le32(hw->txd_cmd | length); in _e1000_transmit()
5179 E1000_WRITE_REG(hw, TDT, tx_tail); in _e1000_transmit()
5181 E1000_WRITE_FLUSH(hw); in _e1000_transmit()
5196 _e1000_disable(struct e1000_hw *hw) in _e1000_disable() argument
5199 E1000_WRITE_REG(hw, RCTL, 0); in _e1000_disable()
5200 E1000_WRITE_REG(hw, TCTL, 0); in _e1000_disable()
5203 E1000_WRITE_REG(hw, TDH, 0); in _e1000_disable()
5204 E1000_WRITE_REG(hw, TDT, 0); in _e1000_disable()
5207 E1000_WRITE_REG(hw, RDH, 0); in _e1000_disable()
5208 E1000_WRITE_REG(hw, RDT, 0); in _e1000_disable()
5215 e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6]) in e1000_reset() argument
5217 e1000_reset_hw(hw); in e1000_reset()
5218 if (hw->mac_type >= e1000_82544) in e1000_reset()
5219 E1000_WRITE_REG(hw, WUC, 0); in e1000_reset()
5221 return e1000_init_hw(hw, enetaddr); in e1000_reset()
5225 _e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6]) in _e1000_init() argument
5229 ret_val = e1000_reset(hw, enetaddr); in _e1000_init()
5233 E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val); in _e1000_init()
5235 E1000_ERR(hw, "Hardware Initialization Failed\n"); in _e1000_init()
5239 e1000_configure_tx(hw); in _e1000_init()
5240 e1000_setup_rctl(hw); in _e1000_init()
5241 e1000_configure_rx(hw); in _e1000_init()
5250 void e1000_get_bus_type(struct e1000_hw *hw) in e1000_get_bus_type() argument
5254 switch (hw->mac_type) { in e1000_get_bus_type()
5257 hw->bus_type = e1000_bus_type_pci; in e1000_get_bus_type()
5266 hw->bus_type = e1000_bus_type_pci_express; in e1000_get_bus_type()
5269 status = E1000_READ_REG(hw, STATUS); in e1000_get_bus_type()
5270 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? in e1000_get_bus_type()
5282 static int e1000_init_one(struct e1000_hw *hw, int cardnum, in e1000_init_one() argument
5285 static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno, in e1000_init_one()
5293 hw->pdev = devno; in e1000_init_one()
5295 hw->pdev = devno; in e1000_init_one()
5297 hw->cardnum = cardnum; in e1000_init_one()
5305 E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0); in e1000_init_one()
5322 E1000_ERR(hw, "Can't enable I/O memory\n"); in e1000_init_one()
5326 E1000_ERR(hw, "Can't enable bus-mastering\n"); in e1000_init_one()
5331 hw->fc = e1000_fc_default; in e1000_init_one()
5332 hw->original_fc = e1000_fc_default; in e1000_init_one()
5333 hw->autoneg_failed = 0; in e1000_init_one()
5334 hw->autoneg = 1; in e1000_init_one()
5335 hw->get_link_status = true; in e1000_init_one()
5337 hw->eeprom_semaphore_present = true; in e1000_init_one()
5340 hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0, in e1000_init_one()
5343 hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, in e1000_init_one()
5346 hw->mac_type = e1000_undefined; in e1000_init_one()
5349 if (e1000_sw_init(hw) < 0) { in e1000_init_one()
5350 E1000_ERR(hw, "Software init failed\n"); in e1000_init_one()
5353 if (e1000_check_phy_reset_block(hw)) in e1000_init_one()
5354 E1000_ERR(hw, "PHY Reset is blocked!\n"); in e1000_init_one()
5357 e1000_reset_hw(hw); in e1000_init_one()
5361 if (e1000_init_eeprom_params(hw)) { in e1000_init_one()
5362 E1000_ERR(hw, "EEPROM is invalid!\n"); in e1000_init_one()
5365 if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) && in e1000_init_one()
5366 e1000_validate_eeprom_checksum(hw)) in e1000_init_one()
5368 e1000_read_mac_addr(hw, enetaddr); in e1000_init_one()
5370 e1000_get_bus_type(hw); in e1000_init_one()
5396 struct e1000_hw *hw = nic->priv; in e1000_transmit() local
5398 return _e1000_transmit(hw, txpacket, length); in e1000_transmit()
5407 struct e1000_hw *hw = nic->priv; in e1000_disable() local
5409 _e1000_disable(hw); in e1000_disable()
5418 struct e1000_hw *hw = nic->priv; in e1000_init() local
5420 return _e1000_init(hw, nic->enetaddr); in e1000_init()
5426 struct e1000_hw *hw = nic->priv; in e1000_poll() local
5429 len = _e1000_poll(hw); in e1000_poll()
5432 fill_rx(hw); in e1000_poll()
5458 struct e1000_hw *hw = malloc(sizeof(*hw)); in e1000_initialize() local
5459 if (!nic || !hw) { in e1000_initialize()
5462 free(hw); in e1000_initialize()
5468 memset(hw, 0, sizeof(*hw)); in e1000_initialize()
5469 nic->priv = hw; in e1000_initialize()
5473 hw->name = nic->name; in e1000_initialize()
5475 ret = e1000_init_one(hw, i, devno, nic->enetaddr); in e1000_initialize()
5478 list_add_tail(&hw->list_node, &e1000_hw_list); in e1000_initialize()
5480 hw->nic = nic; in e1000_initialize()
5495 struct e1000_hw *hw; in e1000_find_card() local
5497 list_for_each_entry(hw, &e1000_hw_list, list_node) in e1000_find_card()
5498 if (hw->cardnum == cardnum) in e1000_find_card()
5499 return hw; in e1000_find_card()
5517 struct e1000_hw *hw; in do_e1000() local
5536 hw = e1000_find_card(cardnum); in do_e1000()
5537 if (hw) in do_e1000()
5538 mac = hw->nic->enetaddr; in do_e1000()
5553 hw = dev_get_priv(dev); in do_e1000()
5557 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3); in do_e1000()
5582 struct e1000_hw *hw = dev_get_priv(dev); in e1000_eth_start() local
5584 return _e1000_init(hw, plat->enetaddr); in e1000_eth_start()
5589 struct e1000_hw *hw = dev_get_priv(dev); in e1000_eth_stop() local
5591 _e1000_disable(hw); in e1000_eth_stop()
5596 struct e1000_hw *hw = dev_get_priv(dev); in e1000_eth_send() local
5599 ret = _e1000_transmit(hw, packet, length); in e1000_eth_send()
5606 struct e1000_hw *hw = dev_get_priv(dev); in e1000_eth_recv() local
5609 len = _e1000_poll(hw); in e1000_eth_recv()
5618 struct e1000_hw *hw = dev_get_priv(dev); in e1000_free_pkt() local
5620 fill_rx(hw); in e1000_free_pkt()
5628 struct e1000_hw *hw = dev_get_priv(dev); in e1000_eth_probe() local
5631 hw->name = dev->name; in e1000_eth_probe()
5632 ret = e1000_init_one(hw, trailing_strtol(dev->name), in e1000_eth_probe()