Lines Matching +full:eth +full:- +full:ck
4 * SPDX-License-Identifier: GPL-2.0
6 * Portions based on U-Boot's rtl8169.c.
15 * configuration-specific logic. Code that interacts with configuration-
18 * configurations, the core code should be adapted to call all configuration-
26 * AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and
45 #include <asm/mach-imx/sys_proto.h>
54 uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */
56 uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
64 uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
66 uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
70 uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
73 uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */
136 uint32_t unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */
138 uint32_t unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */
176 uint32_t unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */
214 /* These registers are Tegra186-specific */
246 * Warn if the cache-line size is larger than the descriptor size. In such
253 * the driver to allocate descriptors from a pool of non-cached memory.
276 * maintenance on CPUs where the cache-line size exceeds the size of these
279 * therefore need to flush the cache-line containing the descriptor, which
280 * will cause all other descriptors in the same cache-line to be flushed
284 * To work around this, we make use of non-cached memory if available. If
290 * are unlikely to share cache-lines.
315 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); in eqos_inval_desc_tegra186()
358 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); in eqos_inval_buffer_tegra186()
392 return wait_for_bit_le32(&eqos->mac_regs->mdio_address, in eqos_mdio_wait_idle()
400 struct eqos_priv *eqos = bus->priv; in eqos_mdio_read()
404 debug("%s(dev=%p, addr=%x, reg=%d):\n", __func__, eqos->dev, mdio_addr, in eqos_mdio_read()
413 val = readl(&eqos->mac_regs->mdio_address); in eqos_mdio_read()
418 (eqos->config->config_mac_mdio << in eqos_mdio_read()
423 writel(val, &eqos->mac_regs->mdio_address); in eqos_mdio_read()
425 udelay(eqos->config->mdio_wait); in eqos_mdio_read()
433 val = readl(&eqos->mac_regs->mdio_data); in eqos_mdio_read()
444 struct eqos_priv *eqos = bus->priv; in eqos_mdio_write()
448 debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev, in eqos_mdio_write()
457 writel(mdio_val, &eqos->mac_regs->mdio_data); in eqos_mdio_write()
459 val = readl(&eqos->mac_regs->mdio_address); in eqos_mdio_write()
464 (eqos->config->config_mac_mdio << in eqos_mdio_write()
469 writel(val, &eqos->mac_regs->mdio_address); in eqos_mdio_write()
471 udelay(eqos->config->mdio_wait); in eqos_mdio_write()
491 ret = clk_enable(&eqos->clk_slave_bus); in eqos_start_clks_tegra186()
497 ret = clk_enable(&eqos->clk_master_bus); in eqos_start_clks_tegra186()
503 ret = clk_enable(&eqos->clk_rx); in eqos_start_clks_tegra186()
509 ret = clk_enable(&eqos->clk_ptp_ref); in eqos_start_clks_tegra186()
515 ret = clk_set_rate(&eqos->clk_ptp_ref, 125 * 1000 * 1000); in eqos_start_clks_tegra186()
521 ret = clk_enable(&eqos->clk_tx); in eqos_start_clks_tegra186()
533 clk_disable(&eqos->clk_ptp_ref); in eqos_start_clks_tegra186()
535 clk_disable(&eqos->clk_rx); in eqos_start_clks_tegra186()
537 clk_disable(&eqos->clk_master_bus); in eqos_start_clks_tegra186()
539 clk_disable(&eqos->clk_slave_bus); in eqos_start_clks_tegra186()
554 ret = clk_enable(&eqos->clk_master_bus); in eqos_start_clks_stm32()
560 if (clk_valid(&eqos->clk_rx)) { in eqos_start_clks_stm32()
561 ret = clk_enable(&eqos->clk_rx); in eqos_start_clks_stm32()
568 if (clk_valid(&eqos->clk_tx)) { in eqos_start_clks_stm32()
569 ret = clk_enable(&eqos->clk_tx); in eqos_start_clks_stm32()
576 if (clk_valid(&eqos->clk_ck)) { in eqos_start_clks_stm32()
577 ret = clk_enable(&eqos->clk_ck); in eqos_start_clks_stm32()
590 if (clk_valid(&eqos->clk_tx)) in eqos_start_clks_stm32()
591 clk_disable(&eqos->clk_tx); in eqos_start_clks_stm32()
593 if (clk_valid(&eqos->clk_rx)) in eqos_start_clks_stm32()
594 clk_disable(&eqos->clk_rx); in eqos_start_clks_stm32()
596 clk_disable(&eqos->clk_master_bus); in eqos_start_clks_stm32()
615 clk_disable(&eqos->clk_tx); in eqos_stop_clks_tegra186()
616 clk_disable(&eqos->clk_ptp_ref); in eqos_stop_clks_tegra186()
617 clk_disable(&eqos->clk_rx); in eqos_stop_clks_tegra186()
618 clk_disable(&eqos->clk_master_bus); in eqos_stop_clks_tegra186()
619 clk_disable(&eqos->clk_slave_bus); in eqos_stop_clks_tegra186()
632 if (clk_valid(&eqos->clk_tx)) in eqos_stop_clks_stm32()
633 clk_disable(&eqos->clk_tx); in eqos_stop_clks_stm32()
634 if (clk_valid(&eqos->clk_rx)) in eqos_stop_clks_stm32()
635 clk_disable(&eqos->clk_rx); in eqos_stop_clks_stm32()
636 clk_disable(&eqos->clk_master_bus); in eqos_stop_clks_stm32()
637 if (clk_valid(&eqos->clk_ck)) in eqos_stop_clks_stm32()
638 clk_disable(&eqos->clk_ck); in eqos_stop_clks_stm32()
656 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1); in eqos_start_resets_tegra186()
664 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0); in eqos_start_resets_tegra186()
670 ret = reset_assert(&eqos->reset_ctl); in eqos_start_resets_tegra186()
678 ret = reset_deassert(&eqos->reset_ctl); in eqos_start_resets_tegra186()
695 if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) { in eqos_start_resets_stm32()
696 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0); in eqos_start_resets_stm32()
703 udelay(eqos->reset_delays[0]); in eqos_start_resets_stm32()
705 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1); in eqos_start_resets_stm32()
712 udelay(eqos->reset_delays[1]); in eqos_start_resets_stm32()
714 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0); in eqos_start_resets_stm32()
721 udelay(eqos->reset_delays[2]); in eqos_start_resets_stm32()
738 reset_assert(&eqos->reset_ctl); in eqos_stop_resets_tegra186()
739 dm_gpio_set_value(&eqos->phy_reset_gpio, 1); in eqos_stop_resets_tegra186()
750 if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) { in eqos_stop_resets_stm32()
751 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1); in eqos_stop_resets_stm32()
775 setbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl, in eqos_calibrate_pads_tegra186()
780 setbits_le32(&eqos->tegra186_regs->auto_cal_config, in eqos_calibrate_pads_tegra186()
783 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status, in eqos_calibrate_pads_tegra186()
790 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status, in eqos_calibrate_pads_tegra186()
800 clrbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl, in eqos_calibrate_pads_tegra186()
814 clrbits_le32(&eqos->tegra186_regs->auto_cal_config, in eqos_disable_calibration_tegra186()
825 return clk_get_rate(&eqos->clk_slave_bus); in eqos_get_tick_clk_rate_tegra186()
837 return clk_get_rate(&eqos->clk_master_bus); in eqos_get_tick_clk_rate_stm32()
889 setbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM); in eqos_set_full_duplex()
900 clrbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM); in eqos_set_half_duplex()
902 /* WAR: Flush TX queue when switching to half-duplex */ in eqos_set_half_duplex()
903 setbits_le32(&eqos->mtl_regs->txq0_operation_mode, in eqos_set_half_duplex()
915 clrbits_le32(&eqos->mac_regs->configuration, in eqos_set_gmii_speed()
927 setbits_le32(&eqos->mac_regs->configuration, in eqos_set_mii_speed_100()
939 clrsetbits_le32(&eqos->mac_regs->configuration, in eqos_set_mii_speed_10()
955 switch (eqos->phy->speed) { in eqos_set_tx_clk_speed_tegra186()
966 pr_err("invalid speed %d", eqos->phy->speed); in eqos_set_tx_clk_speed_tegra186()
967 return -EINVAL; in eqos_set_tx_clk_speed_tegra186()
970 ret = clk_set_rate(&eqos->clk_tx, rate); in eqos_set_tx_clk_speed_tegra186()
995 switch (eqos->phy->speed) { in eqos_set_tx_clk_speed_imx()
1006 pr_err("invalid speed %d", eqos->phy->speed); in eqos_set_tx_clk_speed_imx()
1007 return -EINVAL; in eqos_set_tx_clk_speed_imx()
1028 if (eqos->phy->duplex) in eqos_adjust_link()
1037 switch (eqos->phy->speed) { in eqos_adjust_link()
1051 pr_err("invalid speed %d", eqos->phy->speed); in eqos_adjust_link()
1052 return -EINVAL; in eqos_adjust_link()
1060 ret = eqos->config->ops->eqos_calibrate_pads(dev); in eqos_adjust_link()
1067 ret = eqos->config->ops->eqos_disable_calibration(dev); in eqos_adjust_link()
1074 ret = eqos->config->ops->eqos_set_tx_clk_speed(dev); in eqos_adjust_link()
1099 * support the case of SW that runs subsequent to U-Boot which expects in eqos_write_hwaddr()
1101 * which must happen irrespective of whether the U-Boot user (or in eqos_write_hwaddr()
1106 * Tegra186, and is likely not valid for any non-PCI instantiation of in eqos_write_hwaddr()
1108 * future-proofing with the expectation the driver will eventually be in eqos_write_hwaddr()
1111 if (!eqos->config->reg_access_always_ok && !eqos->reg_access_ok) in eqos_write_hwaddr()
1115 val = (plat->enetaddr[5] << 8) | in eqos_write_hwaddr()
1116 (plat->enetaddr[4]); in eqos_write_hwaddr()
1117 writel(val, &eqos->mac_regs->address0_high); in eqos_write_hwaddr()
1118 val = (plat->enetaddr[3] << 24) | in eqos_write_hwaddr()
1119 (plat->enetaddr[2] << 16) | in eqos_write_hwaddr()
1120 (plat->enetaddr[1] << 8) | in eqos_write_hwaddr()
1121 (plat->enetaddr[0]); in eqos_write_hwaddr()
1122 writel(val, &eqos->mac_regs->address0_low); in eqos_write_hwaddr()
1133 imx_get_mac_from_fuse(dev->req_seq, pdata->enetaddr); in eqos_read_rom_hwaddr()
1135 return !is_valid_ethaddr(pdata->enetaddr); in eqos_read_rom_hwaddr()
1148 if (eqos->config->ops->eqos_start_clks) { in eqos_init()
1149 ret = eqos->config->ops->eqos_start_clks(dev); in eqos_init()
1156 if (!eqos->mii_reseted) { in eqos_init()
1157 ret = eqos->config->ops->eqos_start_resets(dev); in eqos_init()
1163 eqos->mii_reseted = true; in eqos_init()
1167 eqos->reg_access_ok = true; in eqos_init()
1170 val = readl(&eqos->dma_regs->mode); in eqos_init()
1172 writel(val, &eqos->dma_regs->mode); in eqos_init()
1173 while (limit--) { in eqos_init()
1174 if (!(readl(&eqos->dma_regs->mode) & EQOS_DMA_MODE_SWR)) in eqos_init()
1181 ret = -EAGAIN; in eqos_init()
1185 ret = eqos->config->ops->eqos_calibrate_pads(dev); in eqos_init()
1190 rate = eqos->config->ops->eqos_get_tick_clk_rate(dev); in eqos_init()
1192 val = (rate / 1000000) - 1; in eqos_init()
1193 writel(val, &eqos->mac_regs->us_tic_counter); in eqos_init()
1199 if (!eqos->phy) { in eqos_init()
1200 int addr = -1; in eqos_init()
1207 eqos->phy = phy_connect(eqos->mii, addr, dev, in eqos_init()
1208 eqos->config->ops->eqos_get_interface(dev)); in eqos_init()
1209 if (!eqos->phy) { in eqos_init()
1211 ret = -ENODEV; in eqos_init()
1215 if (eqos->max_speed) { in eqos_init()
1216 ret = phy_set_supported(eqos->phy, eqos->max_speed); in eqos_init()
1223 ret = phy_config(eqos->phy); in eqos_init()
1230 ret = phy_startup(eqos->phy); in eqos_init()
1236 if (!eqos->phy->link) { in eqos_init()
1238 ret = -EINVAL; in eqos_init()
1252 phy_shutdown(eqos->phy); in eqos_init()
1254 eqos->config->ops->eqos_stop_resets(dev); in eqos_init()
1255 eqos->mii_reseted = false; in eqos_init()
1257 if (eqos->config->ops->eqos_stop_clks) in eqos_init()
1258 eqos->config->ops->eqos_stop_clks(dev); in eqos_init()
1271 eqos->tx_desc_idx = 0; in eqos_enable()
1272 eqos->rx_desc_idx = 0; in eqos_enable()
1275 writel(0x60, &eqos->mtl_regs->txq0_quantum_weight - 0x100); in eqos_enable()
1279 setbits_le32(&eqos->mtl_regs->txq0_operation_mode, in eqos_enable()
1285 writel(0x10, &eqos->mtl_regs->txq0_quantum_weight); in eqos_enable()
1288 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode, in eqos_enable()
1294 val = readl(&eqos->mac_regs->hw_feature1); in eqos_enable()
1302 * r/tqs is encoded as (n / 256) - 1. in eqos_enable()
1304 tqs = (128 << tx_fifo_sz) / 256 - 1; in eqos_enable()
1305 rqs = (128 << rx_fifo_sz) / 256 - 1; in eqos_enable()
1307 clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode, in eqos_enable()
1311 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode, in eqos_enable()
1317 if (rqs >= ((4096 / 256) - 1)) { in eqos_enable()
1320 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode, in eqos_enable()
1330 if (rqs == ((4096 / 256) - 1)) { in eqos_enable()
1335 rfd = 0x3; /* Full-3K */ in eqos_enable()
1336 rfa = 0x1; /* Full-1.5K */ in eqos_enable()
1337 } else if (rqs == ((8192 / 256) - 1)) { in eqos_enable()
1338 rfd = 0x6; /* Full-4K */ in eqos_enable()
1339 rfa = 0xa; /* Full-6K */ in eqos_enable()
1340 } else if (rqs == ((16384 / 256) - 1)) { in eqos_enable()
1341 rfd = 0x6; /* Full-4K */ in eqos_enable()
1342 rfa = 0x12; /* Full-10K */ in eqos_enable()
1344 rfd = 0x6; /* Full-4K */ in eqos_enable()
1345 rfa = 0x1E; /* Full-16K */ in eqos_enable()
1348 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode, in eqos_enable()
1361 clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0, in eqos_enable()
1364 eqos->config->config_mac << in eqos_enable()
1367 clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0, in eqos_enable()
1374 setbits_le32(&eqos->mac_regs->unused_0a4, in eqos_enable()
1377 setbits_le32(&eqos->mac_regs->unused_004[1], in eqos_enable()
1382 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl, in eqos_enable()
1385 clrbits_le32(&eqos->mac_regs->txq_prty_map0, in eqos_enable()
1389 clrbits_le32(&eqos->mac_regs->rxq_ctrl2, in eqos_enable()
1393 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl, in eqos_enable()
1395 setbits_le32(&eqos->mac_regs->rx_flow_ctrl, in eqos_enable()
1398 clrsetbits_le32(&eqos->mac_regs->configuration, in eqos_enable()
1411 setbits_le32(&eqos->dma_regs->ch0_tx_control, in eqos_enable()
1415 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control, in eqos_enable()
1421 setbits_le32(&eqos->dma_regs->ch0_control, in eqos_enable()
1426 * FIFO size in tqs is encoded as (n / 256) - 1. in eqos_enable()
1428 * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1. in eqos_enable()
1433 clrsetbits_le32(&eqos->dma_regs->ch0_tx_control, in eqos_enable()
1438 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control, in eqos_enable()
1447 writel(val, &eqos->dma_regs->sysbus_mode); in eqos_enable()
1451 memset(eqos->descs, 0, EQOS_DESCRIPTORS_SIZE); in eqos_enable()
1453 struct eqos_desc *rx_desc = &(eqos->rx_descs[i]); in eqos_enable()
1454 rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf + in eqos_enable()
1456 rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; in eqos_enable()
1458 eqos->config->ops->eqos_flush_desc(rx_desc); in eqos_enable()
1459 eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf + in eqos_enable()
1464 writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress); in eqos_enable()
1465 writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address); in eqos_enable()
1466 writel(EQOS_DESCRIPTORS_TX - 1, in eqos_enable()
1467 &eqos->dma_regs->ch0_txdesc_ring_length); in eqos_enable()
1469 writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress); in eqos_enable()
1470 writel((ulong)eqos->rx_descs, &eqos->dma_regs->ch0_rxdesc_list_address); in eqos_enable()
1471 writel(EQOS_DESCRIPTORS_RX - 1, in eqos_enable()
1472 &eqos->dma_regs->ch0_rxdesc_ring_length); in eqos_enable()
1475 setbits_le32(&eqos->dma_regs->ch0_tx_control, in eqos_enable()
1477 setbits_le32(&eqos->dma_regs->ch0_rx_control, in eqos_enable()
1479 setbits_le32(&eqos->mac_regs->configuration, in eqos_enable()
1489 last_rx_desc = (ulong)&(eqos->rx_descs[(EQOS_DESCRIPTORS_RX - 1)]); in eqos_enable()
1490 writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer); in eqos_enable()
1492 eqos->started = true; in eqos_enable()
1515 if (!eqos->started) in eqos_stop()
1517 eqos->started = false; in eqos_stop()
1518 eqos->reg_access_ok = false; in eqos_stop()
1521 clrbits_le32(&eqos->dma_regs->ch0_tx_control, in eqos_stop()
1526 u32 val = readl(&eqos->mtl_regs->txq0_debug); in eqos_stop()
1535 clrbits_le32(&eqos->mac_regs->configuration, in eqos_stop()
1540 u32 val = readl(&eqos->mtl_regs->rxq0_debug); in eqos_stop()
1550 clrbits_le32(&eqos->dma_regs->ch0_rx_control, in eqos_stop()
1553 if (eqos->phy) { in eqos_stop()
1554 phy_shutdown(eqos->phy); in eqos_stop()
1556 if (eqos->config->ops->eqos_stop_clks) in eqos_stop()
1557 eqos->config->ops->eqos_stop_clks(dev); in eqos_stop()
1571 memcpy(eqos->tx_dma_buf, packet, length); in eqos_send()
1572 eqos->config->ops->eqos_flush_buffer(eqos->tx_dma_buf, length); in eqos_send()
1574 tx_desc = &(eqos->tx_descs[eqos->tx_desc_idx]); in eqos_send()
1575 eqos->tx_desc_idx++; in eqos_send()
1576 eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX; in eqos_send()
1578 tx_desc->des0 = (ulong)eqos->tx_dma_buf; in eqos_send()
1579 tx_desc->des1 = 0; in eqos_send()
1580 tx_desc->des2 = length; in eqos_send()
1586 tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length; in eqos_send()
1587 eqos->config->ops->eqos_flush_desc(tx_desc); in eqos_send()
1589 writel((ulong)(&(eqos->tx_descs[eqos->tx_desc_idx])), in eqos_send()
1590 &eqos->dma_regs->ch0_txdesc_tail_pointer); in eqos_send()
1593 eqos->config->ops->eqos_inval_desc(tx_desc); in eqos_send()
1594 if (!(readl(&tx_desc->des3) & EQOS_DESC3_OWN)) in eqos_send()
1601 return -ETIMEDOUT; in eqos_send()
1612 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]); in eqos_recv()
1613 eqos->config->ops->eqos_inval_desc(rx_desc); in eqos_recv()
1614 if (rx_desc->des3 & EQOS_DESC3_OWN) { in eqos_recv()
1616 return -EAGAIN; in eqos_recv()
1619 *packetp = eqos->rx_dma_buf + in eqos_recv()
1620 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE); in eqos_recv()
1621 length = rx_desc->des3 & 0x7fff; in eqos_recv()
1624 eqos->config->ops->eqos_inval_buffer(*packetp, length); in eqos_recv()
1637 packet_expected = eqos->rx_dma_buf + in eqos_free_pkt()
1638 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE); in eqos_free_pkt()
1642 return -EINVAL; in eqos_free_pkt()
1645 eqos->config->ops->eqos_inval_buffer(packet, length); in eqos_free_pkt()
1647 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]); in eqos_free_pkt()
1649 rx_desc->des0 = 0; in eqos_free_pkt()
1651 eqos->config->ops->eqos_flush_desc(rx_desc); in eqos_free_pkt()
1652 eqos->config->ops->eqos_inval_buffer(packet, length); in eqos_free_pkt()
1653 rx_desc->des0 = (u32)(ulong)packet; in eqos_free_pkt()
1654 rx_desc->des1 = 0; in eqos_free_pkt()
1655 rx_desc->des2 = 0; in eqos_free_pkt()
1661 rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; in eqos_free_pkt()
1662 eqos->config->ops->eqos_flush_desc(rx_desc); in eqos_free_pkt()
1664 writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer); in eqos_free_pkt()
1666 eqos->rx_desc_idx++; in eqos_free_pkt()
1667 eqos->rx_desc_idx %= EQOS_DESCRIPTORS_RX; in eqos_free_pkt()
1679 eqos->descs = eqos_alloc_descs(EQOS_DESCRIPTORS_TX + in eqos_probe_resources_core()
1681 if (!eqos->descs) { in eqos_probe_resources_core()
1683 ret = -ENOMEM; in eqos_probe_resources_core()
1686 eqos->tx_descs = (struct eqos_desc *)eqos->descs; in eqos_probe_resources_core()
1687 eqos->rx_descs = (eqos->tx_descs + EQOS_DESCRIPTORS_TX); in eqos_probe_resources_core()
1688 debug("%s: tx_descs=%p, rx_descs=%p\n", __func__, eqos->tx_descs, in eqos_probe_resources_core()
1689 eqos->rx_descs); in eqos_probe_resources_core()
1691 eqos->tx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_MAX_PACKET_SIZE); in eqos_probe_resources_core()
1692 if (!eqos->tx_dma_buf) { in eqos_probe_resources_core()
1694 ret = -ENOMEM; in eqos_probe_resources_core()
1697 debug("%s: tx_dma_buf=%p\n", __func__, eqos->tx_dma_buf); in eqos_probe_resources_core()
1699 eqos->rx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_RX_BUFFER_SIZE); in eqos_probe_resources_core()
1700 if (!eqos->rx_dma_buf) { in eqos_probe_resources_core()
1702 ret = -ENOMEM; in eqos_probe_resources_core()
1705 debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf); in eqos_probe_resources_core()
1707 eqos->rx_pkt = malloc(EQOS_MAX_PACKET_SIZE); in eqos_probe_resources_core()
1708 if (!eqos->rx_pkt) { in eqos_probe_resources_core()
1710 ret = -ENOMEM; in eqos_probe_resources_core()
1713 debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt); in eqos_probe_resources_core()
1715 eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf, in eqos_probe_resources_core()
1722 free(eqos->rx_dma_buf); in eqos_probe_resources_core()
1724 free(eqos->tx_dma_buf); in eqos_probe_resources_core()
1726 eqos_free_descs(eqos->descs); in eqos_probe_resources_core()
1739 free(eqos->rx_pkt); in eqos_remove_resources_core()
1740 free(eqos->rx_dma_buf); in eqos_remove_resources_core()
1741 free(eqos->tx_dma_buf); in eqos_remove_resources_core()
1742 eqos_free_descs(eqos->descs); in eqos_remove_resources_core()
1756 ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl); in eqos_probe_resources_tegra186()
1762 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0, in eqos_probe_resources_tegra186()
1763 &eqos->phy_reset_gpio, in eqos_probe_resources_tegra186()
1770 ret = clk_get_by_name(dev, "slave_bus", &eqos->clk_slave_bus); in eqos_probe_resources_tegra186()
1776 ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus); in eqos_probe_resources_tegra186()
1782 ret = clk_get_by_name(dev, "rx", &eqos->clk_rx); in eqos_probe_resources_tegra186()
1788 ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref); in eqos_probe_resources_tegra186()
1795 ret = clk_get_by_name(dev, "tx", &eqos->clk_tx); in eqos_probe_resources_tegra186()
1805 clk_free(&eqos->clk_ptp_ref); in eqos_probe_resources_tegra186()
1807 clk_free(&eqos->clk_rx); in eqos_probe_resources_tegra186()
1809 clk_free(&eqos->clk_master_bus); in eqos_probe_resources_tegra186()
1811 clk_free(&eqos->clk_slave_bus); in eqos_probe_resources_tegra186()
1813 dm_gpio_free(dev, &eqos->phy_reset_gpio); in eqos_probe_resources_tegra186()
1815 reset_free(&eqos->reset_ctl); in eqos_probe_resources_tegra186()
1822 /* board-specific Ethernet Interface initializations. */
1838 interface = eqos->config->ops->eqos_get_interface(dev); in eqos_probe_resources_stm32()
1842 return -EINVAL; in eqos_probe_resources_stm32()
1847 return -EINVAL; in eqos_probe_resources_stm32()
1849 eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0); in eqos_probe_resources_stm32()
1851 ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus); in eqos_probe_resources_stm32()
1857 ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx); in eqos_probe_resources_stm32()
1861 ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx); in eqos_probe_resources_stm32()
1866 ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck); in eqos_probe_resources_stm32()
1870 eqos->phyaddr = -1; in eqos_probe_resources_stm32()
1871 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, in eqos_probe_resources_stm32()
1874 /* search "reset-gpios" in phy node */ in eqos_probe_resources_stm32()
1876 "reset-gpios", 0, in eqos_probe_resources_stm32()
1877 &eqos->phy_reset_gpio, in eqos_probe_resources_stm32()
1884 eqos->reset_delays[1] = 2; in eqos_probe_resources_stm32()
1886 eqos->phyaddr = ofnode_read_u32_default(phandle_args.node, in eqos_probe_resources_stm32()
1887 "reg", -1); in eqos_probe_resources_stm32()
1890 if (!dm_gpio_is_valid(&eqos->phy_reset_gpio)) { in eqos_probe_resources_stm32()
1893 if (dev_read_bool(dev, "snps,reset-active-low")) in eqos_probe_resources_stm32()
1896 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0, in eqos_probe_resources_stm32()
1897 &eqos->phy_reset_gpio, reset_flags); in eqos_probe_resources_stm32()
1899 ret = dev_read_u32_array(dev, "snps,reset-delays-us", in eqos_probe_resources_stm32()
1900 eqos->reset_delays, 3); in eqos_probe_resources_stm32()
1902 pr_warn("gpio_request_by_name(snps,reset-gpio) failed: %d", in eqos_probe_resources_stm32()
1917 phy_mode = dev_read_string(dev, "phy-mode"); in eqos_get_interface_stm32()
1937 interface = eqos->config->ops->eqos_get_interface(dev); in eqos_probe_resources_imx()
1941 return -EINVAL; in eqos_probe_resources_imx()
1955 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", in eqos_get_interface_imx()
1970 clk_free(&eqos->clk_tx); in eqos_remove_resources_tegra186()
1971 clk_free(&eqos->clk_ptp_ref); in eqos_remove_resources_tegra186()
1972 clk_free(&eqos->clk_rx); in eqos_remove_resources_tegra186()
1973 clk_free(&eqos->clk_slave_bus); in eqos_remove_resources_tegra186()
1974 clk_free(&eqos->clk_master_bus); in eqos_remove_resources_tegra186()
1976 dm_gpio_free(dev, &eqos->phy_reset_gpio); in eqos_remove_resources_tegra186()
1977 reset_free(&eqos->reset_ctl); in eqos_remove_resources_tegra186()
1991 if (clk_valid(&eqos->clk_tx)) in eqos_remove_resources_stm32()
1992 clk_free(&eqos->clk_tx); in eqos_remove_resources_stm32()
1993 if (clk_valid(&eqos->clk_rx)) in eqos_remove_resources_stm32()
1994 clk_free(&eqos->clk_rx); in eqos_remove_resources_stm32()
1995 clk_free(&eqos->clk_master_bus); in eqos_remove_resources_stm32()
1996 if (clk_valid(&eqos->clk_ck)) in eqos_remove_resources_stm32()
1997 clk_free(&eqos->clk_ck); in eqos_remove_resources_stm32()
2000 if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) in eqos_remove_resources_stm32()
2001 dm_gpio_free(dev, &eqos->phy_reset_gpio); in eqos_remove_resources_stm32()
2021 eqos->dev = dev; in eqos_probe()
2022 eqos->config = (void *)dev_get_driver_data(dev); in eqos_probe()
2024 eqos->regs = dev_read_addr(dev); in eqos_probe()
2025 if (eqos->regs == FDT_ADDR_T_NONE) { in eqos_probe()
2027 return -ENODEV; in eqos_probe()
2029 eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE); in eqos_probe()
2030 eqos->mtl_regs = (void *)(eqos->regs + EQOS_MTL_REGS_BASE); in eqos_probe()
2031 eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE); in eqos_probe()
2032 eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE); in eqos_probe()
2040 ret = eqos->config->ops->eqos_probe_resources(dev); in eqos_probe()
2047 eqos->mii = eth_phy_get_mdio_bus(dev); in eqos_probe()
2049 if (!eqos->mii) { in eqos_probe()
2050 eqos->mii = mdio_alloc(); in eqos_probe()
2051 if (!eqos->mii) { in eqos_probe()
2053 ret = -ENOMEM; in eqos_probe()
2056 eqos->mii->read = eqos_mdio_read; in eqos_probe()
2057 eqos->mii->write = eqos_mdio_write; in eqos_probe()
2058 eqos->mii->priv = eqos; in eqos_probe()
2059 strcpy(eqos->mii->name, dev->name); in eqos_probe()
2061 ret = mdio_register(eqos->mii); in eqos_probe()
2069 eth_phy_set_mdio_bus(dev, eqos->mii); in eqos_probe()
2076 mdio_free(eqos->mii); in eqos_probe()
2078 eqos->config->ops->eqos_remove_resources(dev); in eqos_probe()
2092 mdio_unregister(eqos->mii); in eqos_remove()
2093 mdio_free(eqos->mii); in eqos_remove()
2094 eqos->config->ops->eqos_remove_resources(dev); in eqos_remove()
2214 .compatible = "nvidia,tegra186-eqos",
2218 .compatible = "snps,dwmac-4.20a",
2222 .compatible = "fsl,imx-eqos",