108 static void DM9000_iow(int reg, u8 value);
255 	DM9000_iow(DM9000_GPCR, GPCR_GPIO0_OUT);  in dm9000_reset()
257 	DM9000_iow(DM9000_GPR, 0);  in dm9000_reset()
259 	DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST));  in dm9000_reset()
266 	DM9000_iow(DM9000_NCR, 0);  in dm9000_reset()
267 	DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */  in dm9000_reset()
328 	DM9000_iow(DM9000_NCR, 0x0);  in dm9000_init()
330 	DM9000_iow(DM9000_TCR, 0);  in dm9000_init()
332 	DM9000_iow(DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US);  in dm9000_init()
334 	DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));  in dm9000_init()
336 	DM9000_iow(DM9000_FCR, 0x0);  in dm9000_init()
338 	DM9000_iow(DM9000_SMCR, 0);  in dm9000_init()
340 	DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);  in dm9000_init()
342 	DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);  in dm9000_init()
351 		DM9000_iow(oft, dev->enetaddr[i]);  in dm9000_init()
353 		DM9000_iow(oft, 0xff);  in dm9000_init()
362 	DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);  in dm9000_init()
364 	DM9000_iow(DM9000_IMR, IMR_PAR);  in dm9000_init()
411 	DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */  in dm9000_send()
420 	DM9000_iow(DM9000_TXPLL, length & 0xff);  in dm9000_send()
421 	DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);  in dm9000_send()
424 	DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */  in dm9000_send()
435 	DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */  in dm9000_send()
451 	DM9000_iow(DM9000_GPR, 0x01);	/* Power-Down PHY */  in dm9000_halt()
452 	DM9000_iow(DM9000_IMR, 0x80);	/* Disable all interrupt */  in dm9000_halt()
453 	DM9000_iow(DM9000_RCR, 0x00);	/* Disable RX */  in dm9000_halt()
471 	DM9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */  in dm9000_rx()
483 			DM9000_iow(DM9000_RCR, 0x00);	/* Stop Device */  in dm9000_rx()
484 			DM9000_iow(DM9000_ISR, 0x80);	/* Stop INT request */  in dm9000_rx()
535 	DM9000_iow(DM9000_EPAR, offset);  in dm9000_read_srom_word()
536 	DM9000_iow(DM9000_EPCR, 0x4);  in dm9000_read_srom_word()
538 	DM9000_iow(DM9000_EPCR, 0x0);  in dm9000_read_srom_word()
545 	DM9000_iow(DM9000_EPAR, offset);  in dm9000_write_srom_word()
546 	DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));  in dm9000_write_srom_word()
547 	DM9000_iow(DM9000_EPDRL, (val & 0xff));  in dm9000_write_srom_word()
548 	DM9000_iow(DM9000_EPCR, 0x12);  in dm9000_write_srom_word()
550 	DM9000_iow(DM9000_EPCR, 0);  in dm9000_write_srom_word()
577 DM9000_iow(int reg, u8 value)  in DM9000_iow()  function
592 	DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);  in dm9000_phy_read()
593 	DM9000_iow(DM9000_EPCR, 0xc);	/* Issue phyxcer read command */  in dm9000_phy_read()
595 	DM9000_iow(DM9000_EPCR, 0x0);	/* Clear phyxcer read command */  in dm9000_phy_read()
611 	DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);  in dm9000_phy_write()
614 	DM9000_iow(DM9000_EPDRL, (value & 0xff));  in dm9000_phy_write()
615 	DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));  in dm9000_phy_write()
616 	DM9000_iow(DM9000_EPCR, 0xa);	/* Issue phyxcer write command */  in dm9000_phy_write()
618 	DM9000_iow(DM9000_EPCR, 0x0);	/* Clear phyxcer write command */  in dm9000_phy_write()