141 	struct eth_dma_regs *dma_p = priv->dma_regs_p;  in tx_descs_init()  local
175 	writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);  in tx_descs_init()
181 	struct eth_dma_regs *dma_p = priv->dma_regs_p;  in rx_descs_init()  local
215 	writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);  in rx_descs_init()
267 	struct eth_dma_regs *dma_p = priv->dma_regs_p;  in _dw_eth_halt()  local
270 	writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);  in _dw_eth_halt()
278 	struct eth_dma_regs *dma_p = priv->dma_regs_p;  in designware_eth_init()  local
282 	writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);  in designware_eth_init()
285 	while (readl(&dma_p->busmode) & DMAMAC_SRST) {  in designware_eth_init()
303 	writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);  in designware_eth_init()
306 	writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,  in designware_eth_init()
307 	       &dma_p->opmode);  in designware_eth_init()
309 	writel(readl(&dma_p->opmode) | FLUSHTXFIFO,  in designware_eth_init()
310 	       &dma_p->opmode);  in designware_eth_init()
313 	writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);  in designware_eth_init()
316 	writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);  in designware_eth_init()
348 	struct eth_dma_regs *dma_p = priv->dma_regs_p;  in _dw_eth_send()  local
402 	writel(POLL_DATA, &dma_p->txpolldemand);  in _dw_eth_send()