138 static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring …  variable
347 		tx_ring[i].status = 0;  in dc21x4x_init()
348 		tx_ring[i].des1 = 0;  in dc21x4x_init()
349 		tx_ring[i].buf = 0;  in dc21x4x_init()
352 	tx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &tx_ring[(i+1) % NUM_TX_DESC]));  in dc21x4x_init()
354 		tx_ring[i].next = 0;  in dc21x4x_init()
363 	tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER);  in dc21x4x_init()
367 	OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA);  in dc21x4x_init()
389 	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {  in dc21x4x_send()
396 	tx_ring[tx_new].buf    = cpu_to_le32(phys_to_bus((u32) packet));  in dc21x4x_send()
397 	tx_ring[tx_new].des1   = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);  in dc21x4x_send()
398 	tx_ring[tx_new].status = cpu_to_le32(T_OWN);  in dc21x4x_send()
402 	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {  in dc21x4x_send()
409 	if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {  in dc21x4x_send()
412 			le32_to_cpu(tx_ring[tx_new].status));  in dc21x4x_send()
414 		tx_ring[tx_new].status = 0x0;  in dc21x4x_send()
496 	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {  in send_setup_frame()
503 	tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0]));  in send_setup_frame()
504 	tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN);  in send_setup_frame()
505 	tx_ring[tx_new].status = cpu_to_le32(T_OWN);  in send_setup_frame()
509 	for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {  in send_setup_frame()
516 	if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {  in send_setup_frame()
517 		printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status));  in send_setup_frame()