84 static volatile emac_regs	*adap_emac = (emac_regs *)EMAC_BASE_ADDR;  variable
121 	writel(0, &adap_emac->MACINDEX);  in davinci_eth_set_mac_addr()
129 	writel(mac_hi, &adap_emac->MACADDRHI);  in davinci_eth_set_mac_addr()
132 	       &adap_emac->MACADDRLO);  in davinci_eth_set_mac_addr()
134 	writel(mac_lo, &adap_emac->MACADDRLO);  in davinci_eth_set_mac_addr()
137 	writel(0, &adap_emac->MACHASH1);  in davinci_eth_set_mac_addr()
138 	writel(0, &adap_emac->MACHASH2);  in davinci_eth_set_mac_addr()
141 	writel(mac_hi, &adap_emac->MACSRCADDRHI);  in davinci_eth_set_mac_addr()
142 	writel(mac_lo, &adap_emac->MACSRCADDRLO);  in davinci_eth_set_mac_addr()
299 					&adap_emac->MACCONTROL);  in gen_get_link_speed()
303 					&adap_emac->MACCONTROL);  in gen_get_link_speed()
307 			writel(readl(&adap_emac->MACCONTROL) |  in gen_get_link_speed()
309 					 &adap_emac->MACCONTROL);  in gen_get_link_speed()
311 			writel(readl(&adap_emac->MACCONTROL) &  in gen_get_link_speed()
313 					 &adap_emac->MACCONTROL);  in gen_get_link_speed()
406 			writel(readl(&adap_emac->MACCONTROL) |  in davinci_eth_gigabit_enable()
409 				&adap_emac->MACCONTROL);  in davinci_eth_gigabit_enable()
426 	writel(1, &adap_emac->SOFTRESET);  in davinci_eth_open()
427 	while (readl(&adap_emac->SOFTRESET) != 0)  in davinci_eth_open()
448 	writel(1, &adap_emac->TXCONTROL);  in davinci_eth_open()
449 	writel(1, &adap_emac->RXCONTROL);  in davinci_eth_open()
454 	addr = &adap_emac->TX0HDP;  in davinci_eth_open()
458 	addr = &adap_emac->RX0HDP;  in davinci_eth_open()
463 	addr = &adap_emac->RXGOODFRAMES;  in davinci_eth_open()
468 	writel(0, &adap_emac->MACHASH1);  in davinci_eth_open()
469 	writel(0, &adap_emac->MACHASH2);  in davinci_eth_open()
488 	writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN);  in davinci_eth_open()
489 	writel(0, &adap_emac->RXBUFFEROFFSET);  in davinci_eth_open()
495 	writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE);  in davinci_eth_open()
498 	writel(1, &adap_emac->RXUNICASTSET);  in davinci_eth_open()
531 	writel(mac_control, &adap_emac->MACCONTROL);  in davinci_eth_open()
533 	writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP);  in davinci_eth_open()
550 		writel(0, &adap_emac->TXTEARDOWN);  in davinci_eth_ch_teardown()
563 			cnt = readl(&adap_emac->TX0CP);  in davinci_eth_ch_teardown()
565 		writel(cnt, &adap_emac->TX0CP);  in davinci_eth_ch_teardown()
566 		writel(0, &adap_emac->TX0HDP);  in davinci_eth_ch_teardown()
569 		writel(0, &adap_emac->RXTEARDOWN);  in davinci_eth_ch_teardown()
582 			cnt = readl(&adap_emac->RX0CP);  in davinci_eth_ch_teardown()
584 		writel(cnt, &adap_emac->RX0CP);  in davinci_eth_ch_teardown()
585 		writel(0, &adap_emac->RX0HDP);  in davinci_eth_ch_teardown()
597 	if (readl(&adap_emac->RXCONTROL) & 1)  in davinci_eth_close()
601 	writel(1, &adap_emac->SOFTRESET);  in davinci_eth_close()
654 	writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP);  in davinci_eth_send_packet()
663 		if (readl(&adap_emac->TXINTSTATRAW) & 0x01) {  in davinci_eth_send_packet()
702 		writel(BD_TO_HW((ulong)rx_curr_desc), &adap_emac->RX0CP);  in davinci_eth_rcv_packet()
710 				       &adap_emac->RX0HDP);  in davinci_eth_rcv_packet()
728 				       &adap_emac->RX0HDP);  in davinci_eth_rcv_packet()
739 				       &adap_emac->RX0HDP);  in davinci_eth_rcv_packet()