Lines Matching +full:0 +full:x50020000
16 #define GMAC0_REG_BASE 0x18042000
18 #define GMAC0_INT_STATUS_ADDR (GMAC0_REG_BASE + 0x020)
19 #define GMAC0_INTR_RECV_LAZY_ADDR (GMAC0_REG_BASE + 0x100)
20 #define GMAC0_PHY_CTRL_ADDR (GMAC0_REG_BASE + 0x188)
23 #define GMAC_DMA_PTR_OFFSET 0x04
24 #define GMAC_DMA_ADDR_LOW_OFFSET 0x08
25 #define GMAC_DMA_ADDR_HIGH_OFFSET 0x0c
26 #define GMAC_DMA_STATUS0_OFFSET 0x10
27 #define GMAC_DMA_STATUS1_OFFSET 0x14
29 #define GMAC0_DMA_TX_CTRL_ADDR (GMAC0_REG_BASE + 0x200)
41 #define GMAC0_DMA_RX_CTRL_ADDR (GMAC0_REG_BASE + 0x220)
53 #define UNIMAC0_CMD_CFG_ADDR (GMAC0_REG_BASE + 0x808)
54 #define UNIMAC0_MAC_MSB_ADDR (GMAC0_REG_BASE + 0x80c)
55 #define UNIMAC0_MAC_LSB_ADDR (GMAC0_REG_BASE + 0x810)
56 #define UNIMAC0_FRM_LENGTH_ADDR (GMAC0_REG_BASE + 0x814)
62 #define D64_XC_XE 0x00000001
64 #define D64_XC_SE 0x00000002
66 #define D64_XC_PD 0x00000800
68 #define D64_XC_BL_MASK 0x001C0000
73 #define D64_XP_LD_MASK 0x00001fff
77 #define D64_XS0_XS_MASK 0xf0000000
79 #define D64_XS0_XS_DISABLED 0x00000000
80 #define D64_XS0_XS_ACTIVE 0x10000000
81 #define D64_XS0_XS_IDLE 0x20000000
82 #define D64_XS0_XS_STOPPED 0x30000000
83 #define D64_XS0_XS_SUSP 0x40000000
87 #define D64_RC_RE 0x00000001
89 #define D64_RC_AE 0x00030000
91 #define D64_RC_OC 0x00000400
93 #define D64_RC_PD 0x00000800
95 #define D64_RC_RO_MASK 0x000000fe
98 #define D64_RC_BL_MASK 0x001C0000
103 #define DMA_CTRL_PEN (1 << 0)
109 #define D64_RP_LD_MASK 0x00001fff
113 #define D64_RS0_CD_MASK 0x00001fff
115 #define D64_RS0_RS_MASK 0xf0000000
117 #define D64_RS0_RS_DISABLED 0x00000000
118 #define D64_RS0_RS_ACTIVE 0x10000000
119 #define D64_RS0_RS_IDLE 0x20000000
120 #define D64_RS0_RS_STOPPED 0x30000000
121 #define D64_RS0_RS_SUSP 0x40000000
125 #define D64_CTRL_COREFLAGS 0x0ff00000
137 #define D64_CTRL2_BC_MASK 0x00007fff
139 #define D64_CTRL2_AE 0x00030000
142 #define D64_CTRL2_PARITY 0x00040000
144 #define D64_CTRL_CORE_MASK 0x0ff00000
146 #define DC_MROR 0x00000010
147 #define PC_MTE 0x00800000
150 #define CC_TE 0x00000001
151 #define CC_RE 0x00000002
152 #define CC_ES_MASK 0x0000000c
154 #define CC_PROM 0x00000010
155 #define CC_PAD_EN 0x00000020
156 #define CC_CF 0x00000040
157 #define CC_PF 0x00000080
158 #define CC_RPI 0x00000100
159 #define CC_TAI 0x00000200
160 #define CC_HD 0x00000400
162 #define CC_SR 0x00002000
163 #define CC_ML 0x00008000
164 #define CC_AE 0x00400000
165 #define CC_CFE 0x00800000
166 #define CC_NLC 0x01000000
167 #define CC_RL 0x02000000
168 #define CC_RED 0x04000000
169 #define CC_PE 0x08000000
170 #define CC_TPI 0x10000000
171 #define CC_AT 0x20000000
173 #define I_PDEE 0x00000400
174 #define I_PDE 0x00000800
175 #define I_DE 0x00001000
176 #define I_RDU 0x00002000
177 #define I_RFO 0x00004000
178 #define I_XFU 0x00008000
179 #define I_RI 0x00010000
180 #define I_XI0 0x01000000
181 #define I_XI1 0x02000000
182 #define I_XI2 0x04000000
183 #define I_XI3 0x08000000
187 #define I_INTMASK 0x0f01fcff
189 #define CHIP_DRU_BASE 0x0301d000
190 #define CRMU_CHIP_IO_PAD_CONTROL_ADDR (CHIP_DRU_BASE + 0x0bc)
191 #define SWITCH_GLOBAL_CONFIG_ADDR (CHIP_DRU_BASE + 0x194)
193 #define CDRU_IOMUX_FORCE_PAD_IN_SHIFT 0
196 #define AMAC0_IDM_RESET_ADDR 0x18110800
197 #define AMAC0_IO_CTRL_DIRECT_ADDR 0x18110408
202 #define CHIPA_CHIP_ID_ADDR 0x18000000
203 #define CHIPID (readl(CHIPA_CHIP_ID_ADDR) & 0xFFFF)
204 #define CHIPREV (((readl(CHIPA_CHIP_ID_ADDR) >> 16) & 0xF)
205 #define CHIPSKU (((readl(CHIPA_CHIP_ID_ADDR) >> 20) & 0xF)
207 #define GMAC_MII_CTRL_ADDR 0x18002000
210 #define GMAC_MII_DATA_ADDR 0x18002004
211 #define GMAC_MII_DATA_READ_CMD 0x60020000
212 #define GMAC_MII_DATA_WRITE_CMD 0x50020000