Lines Matching +full:0 +full:x00008000
47 #define DISABLE_JUMBO 0
50 #define DISABLE_BURST 0
52 #define NORMAL_RX_MODE 0
66 #define MAX_RX_SIZE 0x3C00
68 #define MARVELL_ALASKA_PHYSID0 0x141
69 #define MARVELL_88E1118_PHYSID1 0xE40
71 #define CICADA_CIS8201_PHYSID0 0x000F
73 #define MEDIA_AUTO 0
82 #define AUTO_MEDIA 0
86 #define TXDP0 0
91 #define CMD_MAP_SIZE 0x100
94 #define AX88180_MEMORY_SIZE 0x00004000
95 #define START_BASE 0x1000
97 #define RX_BUF_SIZE 0x1000
98 #define TX_BUF_SIZE 0x0F00
104 #define AX88180_MEMORY_SIZE 0x00010000
106 #define RX_BUF_SIZE 0x8000
107 #define TX_BUF_SIZE 0x7C00
109 #define RX_BASE 0x0000
116 #define RX_PACKET_LEN_OFFSET 0
117 #define RX_PAGE_NUM_MASK 0x7FF /* RX pages 0~7FFh */
121 #define DECODE (0)
122 #define DECODE_EN 0x00000001
124 #define CMD (CMD_BASE + 0x0000)
125 #define WAKEMOD 0x00000001
126 #define TXEN 0x00000100
127 #define RXEN 0x00000200
129 #define IMR (CMD_BASE + 0x0004)
130 #define IMR_RXBUFFOVR 0x00000001
131 #define IMR_WATCHDOG 0x00000002
132 #define IMR_TX 0x00000008
133 #define IMR_RX 0x00000010
134 #define IMR_PHY 0x00000020
135 #define CLEAR_IMR 0x00000000
138 #define ISR (CMD_BASE + 0x0008)
139 #define ISR_RXBUFFOVR 0x00000001
140 #define ISR_WATCHDOG 0x00000002
141 #define ISR_TX 0x00000008
142 #define ISR_RX 0x00000010
143 #define ISR_PHY 0x00000020
144 #define TXCFG (CMD_BASE + 0x0010)
145 #define AUTOPAD_CRC 0x00000050
147 #define TXCMD (CMD_BASE + 0x0014)
148 #define TXCMD_TXDP_MASK 0x00006000
149 #define TXCMD_TXDP0 0x00000000
150 #define TXCMD_TXDP1 0x00002000
151 #define TXCMD_TXDP2 0x00004000
152 #define TXCMD_TXDP3 0x00006000
153 #define TX_START_WRITE 0x00008000
154 #define TX_STOP_WRITE 0x00000000
155 #define DEFAULT_TXCMD 0x00000000
156 #define TXBS (CMD_BASE + 0x0018)
157 #define TXDP0_USED 0x00000001
158 #define TXDP1_USED 0x00000002
159 #define TXDP2_USED 0x00000004
160 #define TXDP3_USED 0x00000008
161 #define DEFAULT_TXBS 0x00000000
162 #define TXDES0 (CMD_BASE + 0x0020)
163 #define TXDPx_ENABLE 0x00008000
164 #define TXDPx_LEN_MASK 0x00001FFF
165 #define DEFAULT_TXDES0 0x00000000
166 #define TXDES1 (CMD_BASE + 0x0024)
167 #define TXDPx_ENABLE 0x00008000
168 #define TXDPx_LEN_MASK 0x00001FFF
169 #define DEFAULT_TXDES1 0x00000000
170 #define TXDES2 (CMD_BASE + 0x0028)
171 #define TXDPx_ENABLE 0x00008000
172 #define TXDPx_LEN_MASK 0x00001FFF
173 #define DEFAULT_TXDES2 0x00000000
174 #define TXDES3 (CMD_BASE + 0x002C)
175 #define TXDPx_ENABLE 0x00008000
176 #define TXDPx_LEN_MASK 0x00001FFF
177 #define DEFAULT_TXDES3 0x00000000
178 #define RXCFG (CMD_BASE + 0x0030)
179 #define RXBUFF_PROTECT 0x00000001
180 #define RXTCPCRC_CHECK 0x00000010
181 #define RXFLOW_ENABLE 0x00000100
183 #define RXCURT (CMD_BASE + 0x0034)
184 #define DEFAULT_RXCURT 0x00000000
185 #define RXBOUND (CMD_BASE + 0x0038)
186 #define DEFAULT_RXBOUND 0x7FF /* RX pages 0~7FFh */
187 #define MACCFG0 (CMD_BASE + 0x0040)
188 #define MACCFG0_BIT3_0 0x00000007
189 #define IPGT_VAL 0x00000150
190 #define TXFLOW_ENABLE 0x00001000
191 #define SPEED100 0x00008000
193 #define MACCFG1 (CMD_BASE + 0x0044)
194 #define RGMII_EN 0x00000002
195 #define RXFLOW_EN 0x00000020
196 #define FULLDUPLEX 0x00000040
197 #define MAX_JUMBO_LEN 0x00000780
198 #define RXJUMBO_EN 0x00000800
199 #define GIGA_MODE_EN 0x00001000
200 #define RXCRC_CHECK 0x00002000
201 #define RXPAUSE_DA_CHECK 0x00004000
203 #define JUMBO_LEN_4K 0x00000200
204 #define JUMBO_LEN_15K 0x00000780
208 #define MACCFG2 (CMD_BASE + 0x0048)
209 #define MACCFG2_BIT15_8 0x00000100
210 #define JAM_LIMIT_MASK 0x000000FC
211 #define DEFAULT_JAM_LIMIT 0x00000064
213 #define MACCFG3 (CMD_BASE + 0x004C)
214 #define IPGR2_VAL 0x0000000E
215 #define IPGR1_VAL 0x00000600
216 #define NOABORT 0x00008000
218 #define TXPAUT (CMD_BASE + 0x0054)
219 #define DEFAULT_TXPAUT 0x001FE000
220 #define RXBTHD0 (CMD_BASE + 0x0058)
221 #define DEFAULT_RXBTHD0 0x00000300
222 #define RXBTHD1 (CMD_BASE + 0x005C)
223 #define DEFAULT_RXBTHD1 0x00000600
224 #define RXFULTHD (CMD_BASE + 0x0060)
225 #define DEFAULT_RXFULTHD 0x00000100
226 #define MISC (CMD_BASE + 0x0068)
228 #define MISC_NORMAL 0x00000003
229 /* Clear bit 0 to reset MAC */
230 #define MISC_RESET_MAC 0x00000002
232 #define MISC_RESET_PHY 0x00000001
233 /* Clear bit 0 and 1 to reset MAC and PHY */
234 #define MISC_RESET_MAC_PHY 0x00000000
236 #define MACID0 (CMD_BASE + 0x0070)
237 #define MACID1 (CMD_BASE + 0x0074)
238 #define MACID2 (CMD_BASE + 0x0078)
239 #define TXLEN (CMD_BASE + 0x007C)
240 #define DEFAULT_TXLEN 0x000005FC
241 #define RXFILTER (CMD_BASE + 0x0080)
242 #define RX_RXANY 0x00000001
243 #define RX_MULTICAST 0x00000002
244 #define RX_UNICAST 0x00000004
245 #define RX_BROADCAST 0x00000008
246 #define RX_MULTI_HASH 0x00000010
247 #define DISABLE_RXFILTER 0x00000000
249 #define MDIOCTRL (CMD_BASE + 0x0084)
250 #define PHY_ADDR_MASK 0x0000001F
251 #define REG_ADDR_MASK 0x00001F00
252 #define READ_PHY 0x00004000
253 #define WRITE_PHY 0x00008000
254 #define MDIODP (CMD_BASE + 0x0088)
255 #define GPIOCTRL (CMD_BASE + 0x008C)
256 #define RXINDICATOR (CMD_BASE + 0x0090)
257 #define RX_START_READ 0x00000001
258 #define RX_STOP_READ 0x00000000
260 #define TXST (CMD_BASE + 0x0094)
261 #define MDCCLKPAT (CMD_BASE + 0x00A0)
262 #define RXIPCRCCNT (CMD_BASE + 0x00A4)
263 #define RXCRCCNT (CMD_BASE + 0x00A8)
264 #define TXFAILCNT (CMD_BASE + 0x00AC)
265 #define PROMDP (CMD_BASE + 0x00B0)
266 #define PROMCTRL (CMD_BASE + 0x00B4)
267 #define RELOAD_EEPROM 0x00000200
268 #define MAXRXLEN (CMD_BASE + 0x00B8)
269 #define HASHTAB0 (CMD_BASE + 0x00C0)
270 #define HASHTAB1 (CMD_BASE + 0x00C4)
271 #define HASHTAB2 (CMD_BASE + 0x00C8)
272 #define HASHTAB3 (CMD_BASE + 0x00CC)
273 #define DOGTHD0 (CMD_BASE + 0x00E0)
274 #define DEFAULT_DOGTHD0 0x0000FFFF
275 #define DOGTHD1 (CMD_BASE + 0x00E4)
276 #define START_WATCHDOG_TIMER 0x00008000
277 #define DEFAULT_DOGTHD1 0x00000FFF
278 #define SOFTRST (CMD_BASE + 0x00EC)
279 #define SOFTRST_NORMAL 0x00000003
280 #define SOFTRST_RESET_MAC 0x00000002
283 #define M88_SSR 0x0011
284 #define SSR_SPEED_MASK 0xC000
285 #define SSR_SPEED_1000 0x8000
286 #define SSR_SPEED_100 0x4000
287 #define SSR_SPEED_10 0x0000
288 #define SSR_DUPLEX 0x2000
289 #define SSR_MEDIA_RESOLVED_OK 0x0800
298 #define M88_IER 0x0012
299 #define LINK_CHANGE_INT 0x0400
300 #define M88_ISR 0x0013
301 #define LINK_CHANGE_STATUS 0x0400
302 #define M88E1111_EXT_SCR 0x0014
303 #define RGMII_RXCLK_DELAY 0x0080
304 #define RGMII_TXCLK_DELAY 0x0002
306 #define M88E1111_EXT_SSR 0x001B
307 #define HWCFG_MODE_MASK 0x000F
308 #define RGMII_COPPER_MODE 0x000B
311 #define M88E1118_CR 0x14
312 #define M88E1118_CR_RGMII_RXCLK_DELAY 0x0020
313 #define M88E1118_CR_RGMII_TXCLK_DELAY 0x0010
316 #define M88E1118_LEDCTL 0x10 /* Reg 16 on page 3 */
317 #define M88E1118_LEDCTL_LED2INT 0x200
318 #define M88E1118_LEDCTL_LED2BLNK 0x400
319 #define M88E1118_LEDCTL_LED0DUALMODE1 0xc
320 #define M88E1118_LEDCTL_LED0DUALMODE2 0xd
321 #define M88E1118_LEDCTL_LED0DUALMODE3 0xe
322 #define M88E1118_LEDCTL_LED0DUALMODE4 0xf
326 #define M88E1118_LEDMIX 0x11 /* Reg 17 on page 3 */
327 #define M88E1118_LEDMIX_LED050 0x4
328 #define M88E1118_LEDMIX_LED150 0x8
330 #define M88E1118_PAGE_SEL 0x16 /* Reg page select */
333 #define CIS_IMR 0x0019
334 #define CIS_INT_ENABLE 0x8000
335 #define CIS_LINK_CHANGE_INT 0x2000
336 #define CIS_ISR 0x001A
337 #define CIS_INT_PENDING 0x8000
338 #define CIS_LINK_CHANGE_STATUS 0x2000
339 #define CIS_AUX_CTRL_STATUS 0x001C
340 #define CIS_AUTONEG_COMPLETE 0x8000
341 #define CIS_SPEED_MASK 0x0018
342 #define CIS_SPEED_1000 0x0010
343 #define CIS_SPEED_100 0x0008
344 #define CIS_SPEED_10 0x0000
345 #define CIS_DUPLEX 0x0020
354 #define CIS_SMI_PRIORITY 0x0004