Lines Matching refs:ret
159 int ret; in ag7xxx_switch_read() local
167 ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND, in ag7xxx_switch_read()
169 if (ret) in ag7xxx_switch_read()
170 return ret; in ag7xxx_switch_read()
182 int ret; in ag7xxx_switch_write() local
188 ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND, in ag7xxx_switch_write()
191 return ret; in ag7xxx_switch_write()
202 int ret; in ag7xxx_switch_reg_read() local
213 ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9); in ag7xxx_switch_reg_read()
214 if (ret) in ag7xxx_switch_reg_read()
215 return ret; in ag7xxx_switch_reg_read()
221 ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 0, &rv); in ag7xxx_switch_reg_read()
222 if (ret < 0) in ag7xxx_switch_reg_read()
223 return ret; in ag7xxx_switch_reg_read()
226 ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, &rv); in ag7xxx_switch_reg_read()
227 if (ret < 0) in ag7xxx_switch_reg_read()
228 return ret; in ag7xxx_switch_reg_read()
241 int ret; in ag7xxx_switch_reg_write() local
252 ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9); in ag7xxx_switch_reg_write()
253 if (ret) in ag7xxx_switch_reg_write()
254 return ret; in ag7xxx_switch_reg_write()
268 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff); in ag7xxx_switch_reg_write()
269 if (ret < 0) in ag7xxx_switch_reg_write()
270 return ret; in ag7xxx_switch_reg_write()
272 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16); in ag7xxx_switch_reg_write()
273 if (ret < 0) in ag7xxx_switch_reg_write()
274 return ret; in ag7xxx_switch_reg_write()
276 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16); in ag7xxx_switch_reg_write()
277 if (ret < 0) in ag7xxx_switch_reg_write()
278 return ret; in ag7xxx_switch_reg_write()
280 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff); in ag7xxx_switch_reg_write()
281 if (ret < 0) in ag7xxx_switch_reg_write()
282 return ret; in ag7xxx_switch_reg_write()
292 int ret; in ag7xxx_mdio_rw() local
297 ret = ag7xxx_switch_reg_read(bus, 0x98, &data); in ag7xxx_mdio_rw()
298 if (ret < 0) in ag7xxx_mdio_rw()
299 return ret; in ag7xxx_mdio_rw()
301 ret = ag7xxx_switch_reg_write(bus, 0x98, data); in ag7xxx_mdio_rw()
302 if (ret < 0) in ag7xxx_mdio_rw()
303 return ret; in ag7xxx_mdio_rw()
309 ret = ag7xxx_switch_reg_read(bus, 0x98, &data); in ag7xxx_mdio_rw()
310 if (ret < 0) in ag7xxx_mdio_rw()
311 return ret; in ag7xxx_mdio_rw()
328 int ret; in ag7xxx_mdio_write() local
330 ret = ag7xxx_mdio_rw(bus, addr, reg, val); in ag7xxx_mdio_write()
331 if (ret < 0) in ag7xxx_mdio_write()
332 return ret; in ag7xxx_mdio_write()
593 int i, ret, div = ag7xxx_mii_get_div(); in ag7xxx_mii_setup() local
615 ret = ag7xxx_switch_reg_read(priv->bus, 0x10c, ®); in ag7xxx_mii_setup()
616 if (ret) in ag7xxx_mii_setup()
639 int i, ret; in ag933x_phy_setup_lan() local
643 ret = ag7xxx_switch_reg_read(priv->bus, 0, ®); in ag933x_phy_setup_lan()
644 if (ret) in ag933x_phy_setup_lan()
645 return ret; in ag933x_phy_setup_lan()
647 ret = ag7xxx_switch_reg_write(priv->bus, 0, reg); in ag933x_phy_setup_lan()
648 if (ret) in ag933x_phy_setup_lan()
649 return ret; in ag933x_phy_setup_lan()
652 ret = ag7xxx_switch_reg_read(priv->bus, 0, ®); in ag933x_phy_setup_lan()
653 if (ret) in ag933x_phy_setup_lan()
654 return ret; in ag933x_phy_setup_lan()
659 ret = ag7xxx_mdio_write(priv->bus, 0x4, 0, MII_BMCR, 0x9000); in ag933x_phy_setup_lan()
660 if (ret) in ag933x_phy_setup_lan()
661 return ret; in ag933x_phy_setup_lan()
665 ret = ag7xxx_switch_reg_write(priv->bus, 0x78, BIT(8)); in ag933x_phy_setup_lan()
666 if (ret) in ag933x_phy_setup_lan()
667 return ret; in ag933x_phy_setup_lan()
670 ret = ag7xxx_switch_reg_write(priv->bus, i * 0x100, BIT(9)); in ag933x_phy_setup_lan()
671 if (ret) in ag933x_phy_setup_lan()
672 return ret; in ag933x_phy_setup_lan()
676 ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e); in ag933x_phy_setup_lan()
677 if (ret) in ag933x_phy_setup_lan()
678 return ret; in ag933x_phy_setup_lan()
681 ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004); in ag933x_phy_setup_lan()
682 if (ret) in ag933x_phy_setup_lan()
683 return ret; in ag933x_phy_setup_lan()
686 ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50); in ag933x_phy_setup_lan()
687 if (ret) in ag933x_phy_setup_lan()
688 return ret; in ag933x_phy_setup_lan()
691 ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, ®); in ag933x_phy_setup_lan()
692 if (ret) in ag933x_phy_setup_lan()
693 return ret; in ag933x_phy_setup_lan()
695 ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg); in ag933x_phy_setup_lan()
696 if (ret) in ag933x_phy_setup_lan()
697 return ret; in ag933x_phy_setup_lan()
705 int ret; in ag933x_phy_setup_reset_set() local
707 ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_ADVERTISE, in ag933x_phy_setup_reset_set()
710 if (ret) in ag933x_phy_setup_reset_set()
711 return ret; in ag933x_phy_setup_reset_set()
714 ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_CTRL1000, in ag933x_phy_setup_reset_set()
716 if (ret) in ag933x_phy_setup_reset_set()
717 return ret; in ag933x_phy_setup_reset_set()
727 int ret; in ag933x_phy_setup_reset_fin() local
730 ret = ag7xxx_mdio_read(priv->bus, port, 0, MII_BMCR); in ag933x_phy_setup_reset_fin()
731 if (ret < 0) in ag933x_phy_setup_reset_fin()
732 return ret; in ag933x_phy_setup_reset_fin()
734 } while (ret & BMCR_RESET); in ag933x_phy_setup_reset_fin()
742 int i, ret, phymax; in ag933x_phy_setup_common() local
752 ret = ag933x_phy_setup_reset_set(dev, phymax); in ag933x_phy_setup_common()
753 if (ret) in ag933x_phy_setup_common()
754 return ret; in ag933x_phy_setup_common()
756 ret = ag933x_phy_setup_reset_fin(dev, phymax); in ag933x_phy_setup_common()
757 if (ret) in ag933x_phy_setup_common()
758 return ret; in ag933x_phy_setup_common()
761 ret = ag7xxx_mdio_read(priv->bus, phymax, 0, MII_MIPSCR); in ag933x_phy_setup_common()
762 if (ret < 0) in ag933x_phy_setup_common()
763 return ret; in ag933x_phy_setup_common()
770 ret = ag933x_phy_setup_reset_set(dev, i); in ag933x_phy_setup_common()
771 if (ret) in ag933x_phy_setup_common()
772 return ret; in ag933x_phy_setup_common()
776 ret = ag933x_phy_setup_reset_fin(dev, i); in ag933x_phy_setup_common()
777 if (ret) in ag933x_phy_setup_common()
778 return ret; in ag933x_phy_setup_common()
783 ret = ag7xxx_mdio_read(priv->bus, i, 0, MII_MIPSCR); in ag933x_phy_setup_common()
784 if (ret < 0) in ag933x_phy_setup_common()
785 return ret; in ag933x_phy_setup_common()
794 int i, ret; in ag934x_phy_setup() local
797 ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f); in ag934x_phy_setup()
798 if (ret) in ag934x_phy_setup()
799 return ret; in ag934x_phy_setup()
800 ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x40000000); in ag934x_phy_setup()
801 if (ret) in ag934x_phy_setup()
802 return ret; in ag934x_phy_setup()
803 ret = ag7xxx_switch_reg_write(priv->bus, 0x4, 0x07600000); in ag934x_phy_setup()
804 if (ret) in ag934x_phy_setup()
805 return ret; in ag934x_phy_setup()
806 ret = ag7xxx_switch_reg_write(priv->bus, 0xc, 0x01000000); in ag934x_phy_setup()
807 if (ret) in ag934x_phy_setup()
808 return ret; in ag934x_phy_setup()
809 ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e); in ag934x_phy_setup()
810 if (ret) in ag934x_phy_setup()
811 return ret; in ag934x_phy_setup()
814 ret = ag7xxx_switch_reg_read(priv->bus, 0, ®); in ag934x_phy_setup()
815 if (ret) in ag934x_phy_setup()
816 return ret; in ag934x_phy_setup()
819 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x0); in ag934x_phy_setup()
820 if (ret) in ag934x_phy_setup()
821 return ret; in ag934x_phy_setup()
822 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x02ea); in ag934x_phy_setup()
823 if (ret) in ag934x_phy_setup()
824 return ret; in ag934x_phy_setup()
825 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x3d); in ag934x_phy_setup()
826 if (ret) in ag934x_phy_setup()
827 return ret; in ag934x_phy_setup()
828 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x68a0); in ag934x_phy_setup()
829 if (ret) in ag934x_phy_setup()
830 return ret; in ag934x_phy_setup()
834 ret = ag7xxx_switch_reg_read(priv->bus, 0x66c, ®); in ag934x_phy_setup()
835 if (ret) in ag934x_phy_setup()
836 return ret; in ag934x_phy_setup()
838 ret = ag7xxx_switch_reg_write(priv->bus, 0x66c, reg); in ag934x_phy_setup()
839 if (ret) in ag934x_phy_setup()
840 return ret; in ag934x_phy_setup()
848 int ret; in ag7xxx_mac_probe() local
851 ret = ag7xxx_mii_setup(dev); in ag7xxx_mac_probe()
852 if (ret) in ag7xxx_mac_probe()
853 return ret; in ag7xxx_mac_probe()
859 ret = ag933x_phy_setup_wan(dev); in ag7xxx_mac_probe()
861 ret = ag933x_phy_setup_lan(dev); in ag7xxx_mac_probe()
863 ret = ag934x_phy_setup(dev); in ag7xxx_mac_probe()
868 if (ret) in ag7xxx_mac_probe()
869 return ret; in ag7xxx_mac_probe()
923 int ret, phyreg; in ag7xxx_eth_probe() local
926 ret = ag7xxx_get_phy_iface_offset(dev); in ag7xxx_eth_probe()
927 if (ret <= 0) in ag7xxx_eth_probe()
928 return ret; in ag7xxx_eth_probe()
929 phyreg = fdtdec_get_int(gd->fdt_blob, ret, "reg", -1); in ag7xxx_eth_probe()
941 ret = ag7xxx_mdio_probe(dev); in ag7xxx_eth_probe()
942 if (ret) in ag7xxx_eth_probe()
943 return ret; in ag7xxx_eth_probe()
947 ret = ag7xxx_mac_probe(dev); in ag7xxx_eth_probe()
948 debug("%s, ret=%d\n", __func__, ret); in ag7xxx_eth_probe()
950 return ret; in ag7xxx_eth_probe()
977 int ret; in ag7xxx_eth_ofdata_to_platdata() local
983 ret = ag7xxx_get_phy_iface_offset(dev); in ag7xxx_eth_ofdata_to_platdata()
984 if (ret <= 0) in ag7xxx_eth_ofdata_to_platdata()
985 return ret; in ag7xxx_eth_ofdata_to_platdata()
987 phy_mode = fdt_getprop(gd->fdt_blob, ret, "phy-mode", NULL); in ag7xxx_eth_ofdata_to_platdata()