18 static struct smi_regs *const smicntl =  variable
92 		if (readl(&smicntl->smi_sr) & TFF)  in smi_wait_xfer_finish()
113 	writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1);  in smi_read_id()
114 	writel(READ_ID, &smicntl->smi_tr);  in smi_read_id()
116 	       &smicntl->smi_cr2);  in smi_read_id()
121 	value = (readl(&smicntl->smi_rr) & 0x00FFFFFF);  in smi_read_id()
123 	writel(readl(&smicntl->smi_sr) & ~TFF, &smicntl->smi_sr);  in smi_read_id()
124 	writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);  in smi_read_id()
178 	ctrlreg1 = readl(&smicntl->smi_cr1);  in smi_read_sr()
181 	writel(readl(&smicntl->smi_cr1) & ~(SW_MODE | WB_MODE),  in smi_read_sr()
182 	       &smicntl->smi_cr1);  in smi_read_sr()
185 	writel((bank << BANKSEL_SHIFT) | RD_STATUS_REG, &smicntl->smi_cr2);  in smi_read_sr()
190 	val = readl(&smicntl->smi_sr);  in smi_read_sr()
193 	writel(ctrlreg1, &smicntl->smi_cr1);  in smi_read_sr()
242 	ctrlreg1 = readl(&smicntl->smi_cr1);  in smi_write_enable()
245 	writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);  in smi_write_enable()
248 	writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2);  in smi_write_enable()
254 	writel(ctrlreg1, &smicntl->smi_cr1);  in smi_write_enable()
278 	       &smicntl->smi_cr1);  in smi_init()
315 	writel(readl(&smicntl->smi_sr) & ~(ERF1 | ERF2), &smicntl->smi_sr);  in smi_sector_erase()
326 	writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1);  in smi_sector_erase()
329 	writel(instruction, &smicntl->smi_tr);  in smi_sector_erase()
331 		       &smicntl->smi_cr2);  in smi_sector_erase()
339 	writel(readl(&smicntl->smi_cr1) & ~SW_MODE,  in smi_sector_erase()
340 		       &smicntl->smi_cr1);  in smi_sector_erase()
383 	writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);  in smi_write()
412 		if ((readl(&smicntl->smi_sr) & (ERF1 | ERF2)))  in smi_write()
419 	writel(readl(&smicntl->smi_sr) & ~(WCF), &smicntl->smi_sr);  in smi_write()