Lines Matching full:info
123 #define nand_writel(info, off, val) \ argument
124 writel((val), (info)->mmio_base + (off))
126 #define nand_readl(info, off) \ argument
127 readl((info)->mmio_base + (off))
424 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_set_timing() local
439 info->ndtr0cs0 = ndtr0; in pxa3xx_nand_set_timing()
440 info->ndtr1cs0 = ndtr1; in pxa3xx_nand_set_timing()
441 nand_writel(info, NDTR0CS0, ndtr0); in pxa3xx_nand_set_timing()
442 nand_writel(info, NDTR1CS0, ndtr1); in pxa3xx_nand_set_timing()
448 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_set_sdr_timing() local
478 info->ndtr0cs0 = ndtr0; in pxa3xx_nand_set_sdr_timing()
479 info->ndtr1cs0 = ndtr1; in pxa3xx_nand_set_sdr_timing()
480 nand_writel(info, NDTR0CS0, ndtr0); in pxa3xx_nand_set_sdr_timing()
481 nand_writel(info, NDTR1CS0, ndtr1); in pxa3xx_nand_set_sdr_timing()
488 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_init_timings() local
510 dev_err(&info->pdev->dev, "Error: timings not found\n"); in pxa3xx_nand_init_timings()
517 info->reg_ndcr |= NDCR_DWIDTH_M; in pxa3xx_nand_init_timings()
521 info->reg_ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0; in pxa3xx_nand_init_timings()
543 static void pxa3xx_nand_start(struct pxa3xx_nand_info *info) in pxa3xx_nand_start() argument
547 ndcr = info->reg_ndcr; in pxa3xx_nand_start()
549 if (info->use_ecc) { in pxa3xx_nand_start()
551 if (info->ecc_bch) in pxa3xx_nand_start()
552 nand_writel(info, NDECCCTRL, 0x1); in pxa3xx_nand_start()
555 if (info->ecc_bch) in pxa3xx_nand_start()
556 nand_writel(info, NDECCCTRL, 0x0); in pxa3xx_nand_start()
561 if (info->use_spare) in pxa3xx_nand_start()
569 nand_writel(info, NDSR, NDSR_MASK); in pxa3xx_nand_start()
570 nand_writel(info, NDCR, 0); in pxa3xx_nand_start()
571 nand_writel(info, NDCR, ndcr); in pxa3xx_nand_start()
574 static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) in disable_int() argument
578 ndcr = nand_readl(info, NDCR); in disable_int()
579 nand_writel(info, NDCR, ndcr | int_mask); in disable_int()
582 static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len) in drain_fifo() argument
584 if (info->ecc_bch && !info->force_raw) { in drain_fifo()
596 readsl(info->mmio_base + NDDB, data, 8); in drain_fifo()
599 while (!(nand_readl(info, NDSR) & NDSR_RDDREQ)) { in drain_fifo()
601 dev_err(&info->pdev->dev, in drain_fifo()
612 readsl(info->mmio_base + NDDB, data, len); in drain_fifo()
615 static void handle_data_pio(struct pxa3xx_nand_info *info) in handle_data_pio() argument
617 int data_len = info->step_chunk_size; in handle_data_pio()
624 if (info->force_raw) in handle_data_pio()
625 data_len += info->step_spare_size + info->ecc_size; in handle_data_pio()
627 switch (info->state) { in handle_data_pio()
629 if (info->step_chunk_size) in handle_data_pio()
630 writesl(info->mmio_base + NDDB, in handle_data_pio()
631 info->data_buff + info->data_buff_pos, in handle_data_pio()
634 if (info->step_spare_size) in handle_data_pio()
635 writesl(info->mmio_base + NDDB, in handle_data_pio()
636 info->oob_buff + info->oob_buff_pos, in handle_data_pio()
637 DIV_ROUND_UP(info->step_spare_size, 4)); in handle_data_pio()
640 if (info->step_chunk_size) in handle_data_pio()
641 drain_fifo(info, in handle_data_pio()
642 info->data_buff + info->data_buff_pos, in handle_data_pio()
645 if (info->force_raw) in handle_data_pio()
648 if (info->step_spare_size) in handle_data_pio()
649 drain_fifo(info, in handle_data_pio()
650 info->oob_buff + info->oob_buff_pos, in handle_data_pio()
651 DIV_ROUND_UP(info->step_spare_size, 4)); in handle_data_pio()
654 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__, in handle_data_pio()
655 info->state); in handle_data_pio()
660 info->data_buff_pos += data_len; in handle_data_pio()
661 info->oob_buff_pos += info->step_spare_size; in handle_data_pio()
664 static void pxa3xx_nand_irq_thread(struct pxa3xx_nand_info *info) in pxa3xx_nand_irq_thread() argument
666 handle_data_pio(info); in pxa3xx_nand_irq_thread()
668 info->state = STATE_CMD_DONE; in pxa3xx_nand_irq_thread()
669 nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ); in pxa3xx_nand_irq_thread()
672 static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info) in pxa3xx_nand_irq() argument
678 if (info->cs == 0) { in pxa3xx_nand_irq()
689 status = nand_readl(info, NDSR); in pxa3xx_nand_irq()
692 info->retcode = ERR_UNCORERR; in pxa3xx_nand_irq()
694 info->retcode = ERR_CORERR; in pxa3xx_nand_irq()
695 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 && in pxa3xx_nand_irq()
696 info->ecc_bch) in pxa3xx_nand_irq()
697 info->ecc_err_cnt = NDSR_ERR_CNT(status); in pxa3xx_nand_irq()
699 info->ecc_err_cnt = 1; in pxa3xx_nand_irq()
706 info->max_bitflips = max_t(unsigned int, in pxa3xx_nand_irq()
707 info->max_bitflips, in pxa3xx_nand_irq()
708 info->ecc_err_cnt); in pxa3xx_nand_irq()
711 info->state = (status & NDSR_RDDREQ) ? in pxa3xx_nand_irq()
714 pxa3xx_nand_irq_thread(info); in pxa3xx_nand_irq()
718 info->state = STATE_CMD_DONE; in pxa3xx_nand_irq()
722 info->state = STATE_READY; in pxa3xx_nand_irq()
731 nand_writel(info, NDSR, status); in pxa3xx_nand_irq()
735 info->state = STATE_CMD_HANDLE; in pxa3xx_nand_irq()
745 nand_writel(info, NDCB0, info->ndcb0); in pxa3xx_nand_irq()
746 nand_writel(info, NDCB0, info->ndcb1); in pxa3xx_nand_irq()
747 nand_writel(info, NDCB0, info->ndcb2); in pxa3xx_nand_irq()
750 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) in pxa3xx_nand_irq()
751 nand_writel(info, NDCB0, info->ndcb3); in pxa3xx_nand_irq()
755 info->cmd_complete = 1; in pxa3xx_nand_irq()
757 info->dev_ready = 1; in pxa3xx_nand_irq()
770 static void set_command_address(struct pxa3xx_nand_info *info, in set_command_address() argument
774 if (page_size < info->chunk_size) { in set_command_address()
775 info->ndcb1 = ((page_addr & 0xFFFFFF) << 8) in set_command_address()
778 info->ndcb2 = 0; in set_command_address()
780 info->ndcb1 = ((page_addr & 0xFFFF) << 16) in set_command_address()
784 info->ndcb2 = (page_addr & 0xFF0000) >> 16; in set_command_address()
786 info->ndcb2 = 0; in set_command_address()
790 static void prepare_start_command(struct pxa3xx_nand_info *info, int command) in prepare_start_command() argument
792 struct pxa3xx_nand_host *host = info->host[info->cs]; in prepare_start_command()
796 info->buf_start = 0; in prepare_start_command()
797 info->buf_count = 0; in prepare_start_command()
798 info->data_buff_pos = 0; in prepare_start_command()
799 info->oob_buff_pos = 0; in prepare_start_command()
800 info->step_chunk_size = 0; in prepare_start_command()
801 info->step_spare_size = 0; in prepare_start_command()
802 info->cur_chunk = 0; in prepare_start_command()
803 info->use_ecc = 0; in prepare_start_command()
804 info->use_spare = 1; in prepare_start_command()
805 info->retcode = ERR_NONE; in prepare_start_command()
806 info->ecc_err_cnt = 0; in prepare_start_command()
807 info->ndcb3 = 0; in prepare_start_command()
808 info->need_wait = 0; in prepare_start_command()
814 if (!info->force_raw) in prepare_start_command()
815 info->use_ecc = 1; in prepare_start_command()
818 info->use_spare = 0; in prepare_start_command()
821 info->ndcb1 = 0; in prepare_start_command()
822 info->ndcb2 = 0; in prepare_start_command()
833 info->buf_count = mtd->writesize + mtd->oobsize; in prepare_start_command()
834 memset(info->data_buff, 0xFF, info->buf_count); in prepare_start_command()
838 static int prepare_set_command(struct pxa3xx_nand_info *info, int command, in prepare_set_command() argument
845 host = info->host[info->cs]; in prepare_set_command()
850 if (info->cs != 0) in prepare_set_command()
851 info->ndcb0 = NDCB0_CSEL; in prepare_set_command()
853 info->ndcb0 = 0; in prepare_set_command()
864 info->buf_start = column; in prepare_set_command()
865 info->ndcb0 |= NDCB0_CMD_TYPE(0) in prepare_set_command()
870 info->buf_start += mtd->writesize; in prepare_set_command()
872 if (info->cur_chunk < info->nfullchunks) { in prepare_set_command()
873 info->step_chunk_size = info->chunk_size; in prepare_set_command()
874 info->step_spare_size = info->spare_size; in prepare_set_command()
876 info->step_chunk_size = info->last_chunk_size; in prepare_set_command()
877 info->step_spare_size = info->last_spare_size; in prepare_set_command()
885 if (info->force_raw) { in prepare_set_command()
886 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8) | in prepare_set_command()
889 info->ndcb3 = info->step_chunk_size + in prepare_set_command()
890 info->step_spare_size + info->ecc_size; in prepare_set_command()
891 } else if (mtd->writesize == info->chunk_size) { in prepare_set_command()
892 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8); in prepare_set_command()
893 } else if (mtd->writesize > info->chunk_size) { in prepare_set_command()
894 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8) in prepare_set_command()
897 info->ndcb3 = info->step_chunk_size + in prepare_set_command()
898 info->step_spare_size; in prepare_set_command()
901 set_command_address(info, mtd->writesize, column, page_addr); in prepare_set_command()
906 info->buf_start = column; in prepare_set_command()
907 set_command_address(info, mtd->writesize, 0, page_addr); in prepare_set_command()
913 if (mtd->writesize > info->chunk_size) { in prepare_set_command()
914 info->ndcb0 |= NDCB0_CMD_TYPE(0x1) in prepare_set_command()
923 if (is_buf_blank(info->data_buff, in prepare_set_command()
929 if (info->cur_chunk < info->nfullchunks) { in prepare_set_command()
930 info->step_chunk_size = info->chunk_size; in prepare_set_command()
931 info->step_spare_size = info->spare_size; in prepare_set_command()
933 info->step_chunk_size = info->last_chunk_size; in prepare_set_command()
934 info->step_spare_size = info->last_spare_size; in prepare_set_command()
938 if (mtd->writesize > info->chunk_size) { in prepare_set_command()
944 info->ndcb0 |= NDCB0_CMD_TYPE(0x1) in prepare_set_command()
947 info->ndcb3 = info->step_chunk_size + in prepare_set_command()
948 info->step_spare_size; in prepare_set_command()
954 if (info->cur_chunk == info->ntotalchunks) { in prepare_set_command()
955 info->ndcb0 = NDCB0_CMD_TYPE(0x1) in prepare_set_command()
958 info->ndcb1 = 0; in prepare_set_command()
959 info->ndcb2 = 0; in prepare_set_command()
960 info->ndcb3 = 0; in prepare_set_command()
963 info->ndcb0 |= NDCB0_CMD_TYPE(0x1) in prepare_set_command()
974 info->buf_count = INIT_BUFFER_SIZE; in prepare_set_command()
975 info->ndcb0 |= NDCB0_CMD_TYPE(0) in prepare_set_command()
979 info->ndcb1 = (column & 0xFF); in prepare_set_command()
980 info->ndcb3 = INIT_BUFFER_SIZE; in prepare_set_command()
981 info->step_chunk_size = INIT_BUFFER_SIZE; in prepare_set_command()
985 info->buf_count = READ_ID_BYTES; in prepare_set_command()
986 info->ndcb0 |= NDCB0_CMD_TYPE(3) in prepare_set_command()
989 info->ndcb1 = (column & 0xFF); in prepare_set_command()
991 info->step_chunk_size = 8; in prepare_set_command()
994 info->buf_count = 1; in prepare_set_command()
995 info->ndcb0 |= NDCB0_CMD_TYPE(4) in prepare_set_command()
999 info->step_chunk_size = 8; in prepare_set_command()
1003 info->ndcb0 |= NDCB0_CMD_TYPE(2) in prepare_set_command()
1009 info->ndcb1 = page_addr; in prepare_set_command()
1010 info->ndcb2 = 0; in prepare_set_command()
1014 info->ndcb0 |= NDCB0_CMD_TYPE(5) in prepare_set_command()
1025 dev_err(&info->pdev->dev, "non-supported command %x\n", in prepare_set_command()
1038 struct pxa3xx_nand_info *info = host->info_data; in nand_cmdfunc() local
1046 if (info->reg_ndcr & NDCR_DWIDTH_M) in nand_cmdfunc()
1054 if (info->cs != host->cs) { in nand_cmdfunc()
1055 info->cs = host->cs; in nand_cmdfunc()
1056 nand_writel(info, NDTR0CS0, info->ndtr0cs0); in nand_cmdfunc()
1057 nand_writel(info, NDTR1CS0, info->ndtr1cs0); in nand_cmdfunc()
1060 prepare_start_command(info, command); in nand_cmdfunc()
1062 info->state = STATE_PREPARED; in nand_cmdfunc()
1063 exec_cmd = prepare_set_command(info, command, 0, column, page_addr); in nand_cmdfunc()
1068 info->cmd_complete = 0; in nand_cmdfunc()
1069 info->dev_ready = 0; in nand_cmdfunc()
1070 info->need_wait = 1; in nand_cmdfunc()
1071 pxa3xx_nand_start(info); in nand_cmdfunc()
1077 status = nand_readl(info, NDSR); in nand_cmdfunc()
1079 pxa3xx_nand_irq(info); in nand_cmdfunc()
1081 if (info->cmd_complete) in nand_cmdfunc()
1085 dev_err(&info->pdev->dev, "Wait timeout!!!\n"); in nand_cmdfunc()
1090 info->state = STATE_IDLE; in nand_cmdfunc()
1099 struct pxa3xx_nand_info *info = host->info_data; in nand_cmdfunc_extended() local
1107 if (info->reg_ndcr & NDCR_DWIDTH_M) in nand_cmdfunc_extended()
1115 if (info->cs != host->cs) { in nand_cmdfunc_extended()
1116 info->cs = host->cs; in nand_cmdfunc_extended()
1117 nand_writel(info, NDTR0CS0, info->ndtr0cs0); in nand_cmdfunc_extended()
1118 nand_writel(info, NDTR1CS0, info->ndtr1cs0); in nand_cmdfunc_extended()
1138 prepare_start_command(info, command); in nand_cmdfunc_extended()
1148 info->need_wait = 1; in nand_cmdfunc_extended()
1149 info->dev_ready = 0; in nand_cmdfunc_extended()
1154 info->state = STATE_PREPARED; in nand_cmdfunc_extended()
1155 exec_cmd = prepare_set_command(info, command, ext_cmd_type, in nand_cmdfunc_extended()
1158 info->need_wait = 0; in nand_cmdfunc_extended()
1159 info->dev_ready = 1; in nand_cmdfunc_extended()
1163 info->cmd_complete = 0; in nand_cmdfunc_extended()
1164 pxa3xx_nand_start(info); in nand_cmdfunc_extended()
1170 status = nand_readl(info, NDSR); in nand_cmdfunc_extended()
1172 pxa3xx_nand_irq(info); in nand_cmdfunc_extended()
1174 if (info->cmd_complete) in nand_cmdfunc_extended()
1178 dev_err(&info->pdev->dev, "Wait timeout!!!\n"); in nand_cmdfunc_extended()
1189 info->cur_chunk++; in nand_cmdfunc_extended()
1192 if (info->cur_chunk == info->ntotalchunks && in nand_cmdfunc_extended()
1200 if (info->cur_chunk == (info->ntotalchunks + 1) && in nand_cmdfunc_extended()
1207 if (info->cur_chunk == info->ntotalchunks - 1) in nand_cmdfunc_extended()
1217 info->cur_chunk == info->ntotalchunks) { in nand_cmdfunc_extended()
1222 info->state = STATE_IDLE; in nand_cmdfunc_extended()
1240 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_read_page_hwecc() local
1246 if (info->retcode == ERR_CORERR && info->use_ecc) { in pxa3xx_nand_read_page_hwecc()
1247 mtd->ecc_stats.corrected += info->ecc_err_cnt; in pxa3xx_nand_read_page_hwecc()
1249 } else if (info->retcode == ERR_UNCORERR && info->ecc_bch) { in pxa3xx_nand_read_page_hwecc()
1264 info->max_bitflips = max_t(unsigned int, in pxa3xx_nand_read_page_hwecc()
1265 info->max_bitflips, bf); in pxa3xx_nand_read_page_hwecc()
1266 info->retcode = ERR_CORERR; in pxa3xx_nand_read_page_hwecc()
1268 info->retcode = ERR_NONE; in pxa3xx_nand_read_page_hwecc()
1271 } else if (info->retcode == ERR_UNCORERR && !info->ecc_bch) { in pxa3xx_nand_read_page_hwecc()
1274 info->retcode = ERR_NONE; in pxa3xx_nand_read_page_hwecc()
1279 return info->max_bitflips; in pxa3xx_nand_read_page_hwecc()
1287 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_read_page_raw() local
1290 if (!info->ecc_bch) in pxa3xx_nand_read_page_raw()
1297 info->force_raw = true; in pxa3xx_nand_read_page_raw()
1300 ecc_off_buf = (info->nfullchunks * info->spare_size) + in pxa3xx_nand_read_page_raw()
1301 info->last_spare_size; in pxa3xx_nand_read_page_raw()
1302 for (chunk = 0; chunk < info->nfullchunks; chunk++) { in pxa3xx_nand_read_page_raw()
1304 buf + (chunk * info->chunk_size), in pxa3xx_nand_read_page_raw()
1305 info->chunk_size); in pxa3xx_nand_read_page_raw()
1308 (chunk * (info->spare_size)), in pxa3xx_nand_read_page_raw()
1309 info->spare_size); in pxa3xx_nand_read_page_raw()
1312 (chunk * (info->ecc_size)), in pxa3xx_nand_read_page_raw()
1313 info->ecc_size - 2); in pxa3xx_nand_read_page_raw()
1316 if (info->ntotalchunks > info->nfullchunks) { in pxa3xx_nand_read_page_raw()
1318 buf + (info->nfullchunks * info->chunk_size), in pxa3xx_nand_read_page_raw()
1319 info->last_chunk_size); in pxa3xx_nand_read_page_raw()
1322 (info->nfullchunks * (info->spare_size)), in pxa3xx_nand_read_page_raw()
1323 info->last_spare_size); in pxa3xx_nand_read_page_raw()
1326 (info->nfullchunks * (info->ecc_size)), in pxa3xx_nand_read_page_raw()
1327 info->ecc_size - 2); in pxa3xx_nand_read_page_raw()
1330 info->force_raw = false; in pxa3xx_nand_read_page_raw()
1349 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_read_byte() local
1352 if (info->buf_start < info->buf_count) in pxa3xx_nand_read_byte()
1354 retval = info->data_buff[info->buf_start++]; in pxa3xx_nand_read_byte()
1363 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_read_word() local
1366 if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) { in pxa3xx_nand_read_word()
1367 retval = *((u16 *)(info->data_buff+info->buf_start)); in pxa3xx_nand_read_word()
1368 info->buf_start += 2; in pxa3xx_nand_read_word()
1377 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_read_buf() local
1378 int real_len = min_t(size_t, len, info->buf_count - info->buf_start); in pxa3xx_nand_read_buf()
1380 memcpy(buf, info->data_buff + info->buf_start, real_len); in pxa3xx_nand_read_buf()
1381 info->buf_start += real_len; in pxa3xx_nand_read_buf()
1389 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_write_buf() local
1390 int real_len = min_t(size_t, len, info->buf_count - info->buf_start); in pxa3xx_nand_write_buf()
1392 memcpy(info->data_buff + info->buf_start, buf, real_len); in pxa3xx_nand_write_buf()
1393 info->buf_start += real_len; in pxa3xx_nand_write_buf()
1405 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_waitfunc() local
1407 if (info->need_wait) { in pxa3xx_nand_waitfunc()
1410 info->need_wait = 0; in pxa3xx_nand_waitfunc()
1416 status = nand_readl(info, NDSR); in pxa3xx_nand_waitfunc()
1418 pxa3xx_nand_irq(info); in pxa3xx_nand_waitfunc()
1420 if (info->dev_ready) in pxa3xx_nand_waitfunc()
1424 dev_err(&info->pdev->dev, "Ready timeout!!!\n"); in pxa3xx_nand_waitfunc()
1432 if (info->retcode == ERR_NONE) in pxa3xx_nand_waitfunc()
1441 static int pxa3xx_nand_config_ident(struct pxa3xx_nand_info *info) in pxa3xx_nand_config_ident() argument
1443 struct pxa3xx_nand_platform_data *pdata = info->pdata; in pxa3xx_nand_config_ident()
1446 info->reg_ndcr = 0x0; /* enable all interrupts */ in pxa3xx_nand_config_ident()
1447 info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; in pxa3xx_nand_config_ident()
1448 info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES); in pxa3xx_nand_config_ident()
1449 info->reg_ndcr |= NDCR_SPARE_EN; in pxa3xx_nand_config_ident()
1454 static void pxa3xx_nand_config_tail(struct pxa3xx_nand_info *info) in pxa3xx_nand_config_tail() argument
1456 struct pxa3xx_nand_host *host = info->host[info->cs]; in pxa3xx_nand_config_tail()
1457 struct mtd_info *mtd = nand_to_mtd(&info->host[info->cs]->chip); in pxa3xx_nand_config_tail()
1460 info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0; in pxa3xx_nand_config_tail()
1461 info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0; in pxa3xx_nand_config_tail()
1462 info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0; in pxa3xx_nand_config_tail()
1465 static void pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info) in pxa3xx_nand_detect_config() argument
1467 struct pxa3xx_nand_platform_data *pdata = info->pdata; in pxa3xx_nand_detect_config()
1468 uint32_t ndcr = nand_readl(info, NDCR); in pxa3xx_nand_detect_config()
1471 info->chunk_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512; in pxa3xx_nand_detect_config()
1472 info->reg_ndcr = ndcr & in pxa3xx_nand_detect_config()
1474 info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; in pxa3xx_nand_detect_config()
1475 info->ndtr0cs0 = nand_readl(info, NDTR0CS0); in pxa3xx_nand_detect_config()
1476 info->ndtr1cs0 = nand_readl(info, NDTR1CS0); in pxa3xx_nand_detect_config()
1479 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info) in pxa3xx_nand_init_buff() argument
1481 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); in pxa3xx_nand_init_buff()
1482 if (info->data_buff == NULL) in pxa3xx_nand_init_buff()
1489 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_sensing() local
1490 struct pxa3xx_nand_platform_data *pdata = info->pdata; in pxa3xx_nand_sensing()
1496 mtd = nand_to_mtd(&info->host[info->cs]->chip); in pxa3xx_nand_sensing()
1500 info->reg_ndcr = 0x0; /* enable all interrupts */ in pxa3xx_nand_sensing()
1501 info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; in pxa3xx_nand_sensing()
1502 info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES); in pxa3xx_nand_sensing()
1503 info->reg_ndcr |= NDCR_SPARE_EN; /* enable spare by default */ in pxa3xx_nand_sensing()
1520 static int pxa_ecc_init(struct pxa3xx_nand_info *info, in pxa_ecc_init() argument
1525 info->nfullchunks = 1; in pxa_ecc_init()
1526 info->ntotalchunks = 1; in pxa_ecc_init()
1527 info->chunk_size = 2048; in pxa_ecc_init()
1528 info->spare_size = 40; in pxa_ecc_init()
1529 info->ecc_size = 24; in pxa_ecc_init()
1535 info->nfullchunks = 1; in pxa_ecc_init()
1536 info->ntotalchunks = 1; in pxa_ecc_init()
1537 info->chunk_size = 512; in pxa_ecc_init()
1538 info->spare_size = 8; in pxa_ecc_init()
1539 info->ecc_size = 8; in pxa_ecc_init()
1549 info->ecc_bch = 1; in pxa_ecc_init()
1550 info->nfullchunks = 1; in pxa_ecc_init()
1551 info->ntotalchunks = 1; in pxa_ecc_init()
1552 info->chunk_size = 2048; in pxa_ecc_init()
1553 info->spare_size = 32; in pxa_ecc_init()
1554 info->ecc_size = 32; in pxa_ecc_init()
1556 ecc->size = info->chunk_size; in pxa_ecc_init()
1561 info->ecc_bch = 1; in pxa_ecc_init()
1562 info->nfullchunks = 2; in pxa_ecc_init()
1563 info->ntotalchunks = 2; in pxa_ecc_init()
1564 info->chunk_size = 2048; in pxa_ecc_init()
1565 info->spare_size = 32; in pxa_ecc_init()
1566 info->ecc_size = 32; in pxa_ecc_init()
1568 ecc->size = info->chunk_size; in pxa_ecc_init()
1573 info->ecc_bch = 1; in pxa_ecc_init()
1574 info->nfullchunks = 4; in pxa_ecc_init()
1575 info->ntotalchunks = 4; in pxa_ecc_init()
1576 info->chunk_size = 2048; in pxa_ecc_init()
1577 info->spare_size = 32; in pxa_ecc_init()
1578 info->ecc_size = 32; in pxa_ecc_init()
1580 ecc->size = info->chunk_size; in pxa_ecc_init()
1589 info->ecc_bch = 1; in pxa_ecc_init()
1590 info->nfullchunks = 1; in pxa_ecc_init()
1591 info->ntotalchunks = 2; in pxa_ecc_init()
1592 info->chunk_size = 1024; in pxa_ecc_init()
1593 info->spare_size = 0; in pxa_ecc_init()
1594 info->last_chunk_size = 1024; in pxa_ecc_init()
1595 info->last_spare_size = 32; in pxa_ecc_init()
1596 info->ecc_size = 32; in pxa_ecc_init()
1598 ecc->size = info->chunk_size; in pxa_ecc_init()
1603 info->ecc_bch = 1; in pxa_ecc_init()
1604 info->nfullchunks = 4; in pxa_ecc_init()
1605 info->ntotalchunks = 5; in pxa_ecc_init()
1606 info->chunk_size = 1024; in pxa_ecc_init()
1607 info->spare_size = 0; in pxa_ecc_init()
1608 info->last_chunk_size = 0; in pxa_ecc_init()
1609 info->last_spare_size = 64; in pxa_ecc_init()
1610 info->ecc_size = 32; in pxa_ecc_init()
1612 ecc->size = info->chunk_size; in pxa_ecc_init()
1617 info->ecc_bch = 1; in pxa_ecc_init()
1618 info->nfullchunks = 8; in pxa_ecc_init()
1619 info->ntotalchunks = 9; in pxa_ecc_init()
1620 info->chunk_size = 1024; in pxa_ecc_init()
1621 info->spare_size = 0; in pxa_ecc_init()
1622 info->last_chunk_size = 0; in pxa_ecc_init()
1623 info->last_spare_size = 160; in pxa_ecc_init()
1624 info->ecc_size = 32; in pxa_ecc_init()
1626 ecc->size = info->chunk_size; in pxa_ecc_init()
1631 dev_err(&info->pdev->dev, in pxa_ecc_init()
1644 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_scan() local
1645 struct pxa3xx_nand_platform_data *pdata = info->pdata; in pxa3xx_nand_scan()
1650 pxa3xx_nand_detect_config(info); in pxa3xx_nand_scan()
1652 ret = pxa3xx_nand_config_ident(info); in pxa3xx_nand_scan()
1657 dev_info(&info->pdev->dev, in pxa3xx_nand_scan()
1659 info->cs); in pxa3xx_nand_scan()
1665 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) in pxa3xx_nand_scan()
1666 nand_writel(info, NDECCCTRL, 0x0); in pxa3xx_nand_scan()
1674 dev_err(&info->pdev->dev, in pxa3xx_nand_scan()
1704 ret = pxa_ecc_init(info, &chip->ecc, ecc_strength, in pxa3xx_nand_scan()
1714 if (mtd->writesize > info->chunk_size) { in pxa3xx_nand_scan()
1715 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) { in pxa3xx_nand_scan()
1718 dev_err(&info->pdev->dev, in pxa3xx_nand_scan()
1731 kfree(info->data_buff); in pxa3xx_nand_scan()
1734 info->buf_size = mtd->writesize + mtd->oobsize; in pxa3xx_nand_scan()
1735 ret = pxa3xx_nand_init_buff(info); in pxa3xx_nand_scan()
1738 info->oob_buff = info->data_buff + mtd->writesize; in pxa3xx_nand_scan()
1746 pxa3xx_nand_config_tail(info); in pxa3xx_nand_scan()
1751 static int alloc_nand_resource(struct pxa3xx_nand_info *info) in alloc_nand_resource() argument
1759 pdata = info->pdata; in alloc_nand_resource()
1763 info->variant = pxa3xx_nand_get_variant(); in alloc_nand_resource()
1766 ((u8 *)&info[1] + sizeof(*host) * cs); in alloc_nand_resource()
1769 info->host[cs] = host; in alloc_nand_resource()
1771 host->info_data = info; in alloc_nand_resource()
1779 chip->controller = &info->controller; in alloc_nand_resource()
1791 info->buf_size = INIT_BUFFER_SIZE; in alloc_nand_resource()
1792 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); in alloc_nand_resource()
1793 if (info->data_buff == NULL) { in alloc_nand_resource()
1799 disable_int(info, NDSR_MASK); in alloc_nand_resource()
1803 kfree(info->data_buff); in alloc_nand_resource()
1808 static int pxa3xx_nand_probe_dt(struct pxa3xx_nand_info *info) in pxa3xx_nand_probe_dt() argument
1830 info->mmio_base = in pxa3xx_nand_probe_dt()
1859 info->pdata = pdata; in pxa3xx_nand_probe_dt()
1869 static int pxa3xx_nand_probe(struct pxa3xx_nand_info *info) in pxa3xx_nand_probe() argument
1874 ret = pxa3xx_nand_probe_dt(info); in pxa3xx_nand_probe()
1878 pdata = info->pdata; in pxa3xx_nand_probe()
1880 ret = alloc_nand_resource(info); in pxa3xx_nand_probe()
1888 struct mtd_info *mtd = nand_to_mtd(&info->host[cs]->chip); in pxa3xx_nand_probe()
1896 info->cs = cs; in pxa3xx_nand_probe()
1921 struct pxa3xx_nand_info *info; in board_nand_init() local
1925 info = kzalloc(sizeof(*info) + in board_nand_init()
1928 if (!info) in board_nand_init()
1931 ret = pxa3xx_nand_probe(info); in board_nand_init()