125 	u32 var;  in xenon_mmc_phy_init()  local
128 	var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);  in xenon_mmc_phy_init()
129 	var |= SAMPL_INV_QSP_PHASE_SELECT;  in xenon_mmc_phy_init()
135 		var |= EMMC_PHY_SLOW_MODE;  in xenon_mmc_phy_init()
136 	sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);  in xenon_mmc_phy_init()
142 		var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);  in xenon_mmc_phy_init()
143 		if (var & SDHCI_CLOCK_INT_STABLE)  in xenon_mmc_phy_init()
155 	var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);  in xenon_mmc_phy_init()
156 	var |= PHY_INITIALIZAION;  in xenon_mmc_phy_init()
157 	sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);  in xenon_mmc_phy_init()
168 		var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);  in xenon_mmc_phy_init()
169 		var &= PHY_INITIALIZAION;  in xenon_mmc_phy_init()
170 		if (!var)  in xenon_mmc_phy_init()
201 	u32 var;  in xenon_mmc_phy_set()  local
204 	var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL);  in xenon_mmc_phy_set()
205 	var |= AUTO_RECEN_CTRL | OEN_QSN | FC_QSP_RECEN |  in xenon_mmc_phy_set()
207 	sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL);  in xenon_mmc_phy_set()
210 	var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL1);  in xenon_mmc_phy_set()
211 	var |= (EMMC5_1_FC_CMD_PU | EMMC5_1_FC_DQ_PU);  in xenon_mmc_phy_set()
212 	var &= ~(EMMC5_1_FC_CMD_PD | EMMC5_1_FC_DQ_PD);  in xenon_mmc_phy_set()
213 	sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL1);  in xenon_mmc_phy_set()
226 		var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST);  in xenon_mmc_phy_set()
227 		var |= OUTPUT_QSN_PHASE_SELECT;  in xenon_mmc_phy_set()
228 		sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST);  in xenon_mmc_phy_set()
235 	var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);  in xenon_mmc_phy_set()
236 	var &= ~SDHCI_CLOCK_CARD_EN;  in xenon_mmc_phy_set()
237 	sdhci_writew(host, var, SDHCI_CLOCK_CONTROL);  in xenon_mmc_phy_set()
239 	var = sdhci_readl(host, EMMC_PHY_FUNC_CONTROL);  in xenon_mmc_phy_set()
241 		var |= (DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | CMD_DDR_MODE;  in xenon_mmc_phy_set()
243 		var &= ~((DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) |  in xenon_mmc_phy_set()
246 	sdhci_writel(host, var, EMMC_PHY_FUNC_CONTROL);  in xenon_mmc_phy_set()
249 	var = sdhci_readl(host, SDHCI_CLOCK_CONTROL);  in xenon_mmc_phy_set()
250 	var |= SDHCI_CLOCK_CARD_EN;  in xenon_mmc_phy_set()
251 	sdhci_writew(host, var, SDHCI_CLOCK_CONTROL);  in xenon_mmc_phy_set()
259 	u32 var;  in xenon_mmc_set_acg()  local
261 	var = sdhci_readl(host, SDHC_SYS_OP_CTRL);  in xenon_mmc_set_acg()
263 		var &= ~AUTO_CLKGATE_DISABLE_MASK;  in xenon_mmc_set_acg()
265 		var |= AUTO_CLKGATE_DISABLE_MASK;  in xenon_mmc_set_acg()
267 	sdhci_writel(host, var, SDHC_SYS_OP_CTRL);  in xenon_mmc_set_acg()
275 	u32 var;  in xenon_mmc_enable_slot()  local
277 	var = sdhci_readl(host, SDHC_SYS_OP_CTRL);  in xenon_mmc_enable_slot()
278 	var |= SLOT_MASK(slot) << SLOT_ENABLE_SHIFT;  in xenon_mmc_enable_slot()
279 	sdhci_writel(host, var, SDHC_SYS_OP_CTRL);  in xenon_mmc_enable_slot()
285 	u32 var;  in xenon_mmc_enable_parallel_tran()  local
287 	var = sdhci_readl(host, SDHC_SYS_EXT_OP_CTRL);  in xenon_mmc_enable_parallel_tran()
288 	var |= SLOT_MASK(slot);  in xenon_mmc_enable_parallel_tran()
289 	sdhci_writel(host, var, SDHC_SYS_EXT_OP_CTRL);  in xenon_mmc_enable_parallel_tran()
294 	u32 var;  in xenon_mmc_disable_tuning()  local
297 	var = sdhci_readl(host, SDHC_SLOT_RETUNING_REQ_CTRL);  in xenon_mmc_disable_tuning()
298 	var &= ~RETUNING_COMPATIBLE;  in xenon_mmc_disable_tuning()
299 	sdhci_writel(host, var, SDHC_SLOT_RETUNING_REQ_CTRL);  in xenon_mmc_disable_tuning()
302 	var = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);  in xenon_mmc_disable_tuning()
303 	var &= ~SDHCI_RETUNE_EVT_INTSIG;  in xenon_mmc_disable_tuning()
304 	sdhci_writel(host, var, SDHCI_SIGNAL_ENABLE);  in xenon_mmc_disable_tuning()