Lines Matching +full:stm32 +full:- +full:timer +full:- +full:counter
2 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
5 * SPDX-License-Identifier: GPL-2.0+
49 #define SDMMC_DTIMER 0x24 /* SDMMC data timer */
52 #define SDMMC_DCOUNT 0x30 /* SDMMC data counter */
198 data_ctrl = (__ilog2(data->blocksize) << in stm32_sdmmc2_start_data()
202 if (data->flags & MMC_DATA_READ) { in stm32_sdmmc2_start_data()
204 idmabase0 = (u32)data->dest; in stm32_sdmmc2_start_data()
206 idmabase0 = (u32)data->src; in stm32_sdmmc2_start_data()
210 writel(SDMMC_CMD_TIMEOUT, priv->base + SDMMC_DTIMER); in stm32_sdmmc2_start_data()
213 writel(ctx->data_length, priv->base + SDMMC_DLEN); in stm32_sdmmc2_start_data()
216 writel(data_ctrl, priv->base + SDMMC_DCTRL); in stm32_sdmmc2_start_data()
219 ctx->cache_start = rounddown(idmabase0, ARCH_DMA_MINALIGN); in stm32_sdmmc2_start_data()
220 ctx->cache_end = roundup(idmabase0 + ctx->data_length, in stm32_sdmmc2_start_data()
226 * Avoid issue on buffer not cached-aligned in stm32_sdmmc2_start_data()
228 flush_dcache_range(ctx->cache_start, ctx->cache_end); in stm32_sdmmc2_start_data()
231 writel(idmabase0, priv->base + SDMMC_IDMABASE0); in stm32_sdmmc2_start_data()
232 writel(SDMMC_IDMACTRL_IDMAEN, priv->base + SDMMC_IDMACTRL); in stm32_sdmmc2_start_data()
238 if (readl(priv->base + SDMMC_ARG) & SDMMC_CMD_CPSMEN) in stm32_sdmmc2_start_cmd()
239 writel(0, priv->base + SDMMC_ARG); in stm32_sdmmc2_start_cmd()
241 cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN; in stm32_sdmmc2_start_cmd()
242 if (cmd->resp_type & MMC_RSP_PRESENT) { in stm32_sdmmc2_start_cmd()
243 if (cmd->resp_type & MMC_RSP_136) in stm32_sdmmc2_start_cmd()
245 else if (cmd->resp_type & MMC_RSP_CRC) in stm32_sdmmc2_start_cmd()
252 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR); in stm32_sdmmc2_start_cmd()
255 writel(cmd->cmdarg, priv->base + SDMMC_ARG); in stm32_sdmmc2_start_cmd()
258 writel(cmd_param, priv->base + SDMMC_CMD); in stm32_sdmmc2_start_cmd()
269 if (cmd->resp_type & MMC_RSP_PRESENT) { in stm32_sdmmc2_end_cmd()
271 if (cmd->resp_type & MMC_RSP_CRC) in stm32_sdmmc2_end_cmd()
278 ret = readl_poll_timeout(priv->base + SDMMC_STA, status, status & mask, in stm32_sdmmc2_end_cmd()
283 ctx->dpsm_abort = true; in stm32_sdmmc2_end_cmd()
290 __func__, status, cmd->cmdidx); in stm32_sdmmc2_end_cmd()
291 ctx->dpsm_abort = true; in stm32_sdmmc2_end_cmd()
292 return -ETIMEDOUT; in stm32_sdmmc2_end_cmd()
295 if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) { in stm32_sdmmc2_end_cmd()
297 __func__, status, cmd->cmdidx); in stm32_sdmmc2_end_cmd()
298 ctx->dpsm_abort = true; in stm32_sdmmc2_end_cmd()
299 return -EILSEQ; in stm32_sdmmc2_end_cmd()
302 if (status & SDMMC_STA_CMDREND && cmd->resp_type & MMC_RSP_PRESENT) { in stm32_sdmmc2_end_cmd()
303 cmd->response[0] = readl(priv->base + SDMMC_RESP1); in stm32_sdmmc2_end_cmd()
304 if (cmd->resp_type & MMC_RSP_136) { in stm32_sdmmc2_end_cmd()
305 cmd->response[1] = readl(priv->base + SDMMC_RESP2); in stm32_sdmmc2_end_cmd()
306 cmd->response[2] = readl(priv->base + SDMMC_RESP3); in stm32_sdmmc2_end_cmd()
307 cmd->response[3] = readl(priv->base + SDMMC_RESP4); in stm32_sdmmc2_end_cmd()
323 if (data->flags & MMC_DATA_READ) in stm32_sdmmc2_end_data()
328 status = readl(priv->base + SDMMC_STA); in stm32_sdmmc2_end_data()
330 status = readl(priv->base + SDMMC_STA); in stm32_sdmmc2_end_data()
334 * cache-refill during the DMA operations (pre-fetching) in stm32_sdmmc2_end_data()
336 if (data->flags & MMC_DATA_READ) in stm32_sdmmc2_end_data()
337 invalidate_dcache_range(ctx->cache_start, ctx->cache_end); in stm32_sdmmc2_end_data()
341 __func__, status, cmd->cmdidx); in stm32_sdmmc2_end_data()
342 if (readl(priv->base + SDMMC_DCOUNT)) in stm32_sdmmc2_end_data()
343 ctx->dpsm_abort = true; in stm32_sdmmc2_end_data()
344 return -EILSEQ; in stm32_sdmmc2_end_data()
349 __func__, status, cmd->cmdidx); in stm32_sdmmc2_end_data()
350 ctx->dpsm_abort = true; in stm32_sdmmc2_end_data()
351 return -ETIMEDOUT; in stm32_sdmmc2_end_data()
356 __func__, status, cmd->cmdidx); in stm32_sdmmc2_end_data()
357 ctx->dpsm_abort = true; in stm32_sdmmc2_end_data()
358 return -EIO; in stm32_sdmmc2_end_data()
363 __func__, status, cmd->cmdidx); in stm32_sdmmc2_end_data()
364 ctx->dpsm_abort = true; in stm32_sdmmc2_end_data()
365 return -EIO; in stm32_sdmmc2_end_data()
370 __func__, status, cmd->cmdidx); in stm32_sdmmc2_end_data()
371 ctx->dpsm_abort = true; in stm32_sdmmc2_end_data()
372 return -EIO; in stm32_sdmmc2_end_data()
391 ctx.data_length = data->blocks * data->blocksize; in stm32_sdmmc2_send_cmd()
398 __func__, cmd->cmdidx, in stm32_sdmmc2_send_cmd()
407 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR); in stm32_sdmmc2_send_cmd()
409 writel(0x0, priv->base + SDMMC_IDMACTRL); in stm32_sdmmc2_send_cmd()
415 if (ctx.dpsm_abort && (cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) { in stm32_sdmmc2_send_cmd()
428 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR); in stm32_sdmmc2_send_cmd()
431 if ((ret != -ETIMEDOUT) && (ret != 0) && retry) { in stm32_sdmmc2_send_cmd()
433 __func__, cmd->cmdidx); in stm32_sdmmc2_send_cmd()
434 retry--; in stm32_sdmmc2_send_cmd()
438 debug("%s: end for CMD %d, ret = %d\n", __func__, cmd->cmdidx, ret); in stm32_sdmmc2_send_cmd()
446 reset_assert(&priv->reset_ctl); in stm32_sdmmc2_pwron()
448 reset_deassert(&priv->reset_ctl); in stm32_sdmmc2_pwron()
453 writel(SDMMC_POWER_PWRCTRL | priv->pwr_reg_msk, priv->base + SDMMC_POWER); in stm32_sdmmc2_pwron()
468 struct mmc_config *cfg = &plat->cfg; in stm32_sdmmc2_set_ios()
469 u32 desired = mmc->clock; in stm32_sdmmc2_set_ios()
470 u32 sys_clock = clk_get_rate(&priv->clk); in stm32_sdmmc2_set_ios()
474 mmc->bus_width, mmc->clock); in stm32_sdmmc2_set_ios()
476 if ((mmc->bus_width == 1) && (desired == cfg->f_min)) in stm32_sdmmc2_set_ios()
487 IS_RISING_EDGE(priv->clk_reg_msk))) { in stm32_sdmmc2_set_ios()
493 if (mmc->bus_width == 4) in stm32_sdmmc2_set_ios()
495 if (mmc->bus_width == 8) in stm32_sdmmc2_set_ios()
498 writel(clk | priv->clk_reg_msk, priv->base + SDMMC_CLKCR); in stm32_sdmmc2_set_ios()
509 if (dm_gpio_is_valid(&priv->cd_gpio)) in stm32_sdmmc2_getcd()
510 return dm_gpio_get_value(&priv->cd_gpio); in stm32_sdmmc2_getcd()
526 struct mmc_config *cfg = &plat->cfg; in stm32_sdmmc2_probe()
529 priv->base = dev_read_addr(dev); in stm32_sdmmc2_probe()
530 if (priv->base == FDT_ADDR_T_NONE) in stm32_sdmmc2_probe()
531 return -EINVAL; in stm32_sdmmc2_probe()
534 priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE; in stm32_sdmmc2_probe()
536 priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL; in stm32_sdmmc2_probe()
538 ret = clk_get_by_index(dev, 0, &priv->clk); in stm32_sdmmc2_probe()
542 ret = clk_enable(&priv->clk); in stm32_sdmmc2_probe()
546 ret = reset_get_by_index(dev, 0, &priv->reset_ctl); in stm32_sdmmc2_probe()
550 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, in stm32_sdmmc2_probe()
553 cfg->f_min = 400000; in stm32_sdmmc2_probe()
554 cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000); in stm32_sdmmc2_probe()
555 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; in stm32_sdmmc2_probe()
556 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; in stm32_sdmmc2_probe()
557 cfg->name = "STM32 SDMMC2"; in stm32_sdmmc2_probe()
559 cfg->host_caps = 0; in stm32_sdmmc2_probe()
560 if (cfg->f_max > 25000000) in stm32_sdmmc2_probe()
561 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; in stm32_sdmmc2_probe()
563 switch (dev_read_u32_default(dev, "bus-width", 1)) { in stm32_sdmmc2_probe()
565 cfg->host_caps |= MMC_MODE_8BIT; in stm32_sdmmc2_probe()
567 cfg->host_caps |= MMC_MODE_4BIT; in stm32_sdmmc2_probe()
572 pr_err("invalid \"bus-width\" property, force to 1\n"); in stm32_sdmmc2_probe()
575 upriv->mmc = &plat->mmc; in stm32_sdmmc2_probe()
580 clk_disable(&priv->clk); in stm32_sdmmc2_probe()
582 clk_free(&priv->clk); in stm32_sdmmc2_probe()
591 return mmc_bind(dev, &plat->mmc, &plat->cfg); in stm32_sdmmc_bind()
595 { .compatible = "st,stm32-sdmmc2" },