5  * SPDX-License-Identifier:	GPL-2.0+
8  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
15 #include <sdhci.h>
23 static void sdhci_reset(struct sdhci_host *host, u8 mask)  in sdhci_reset()  argument
29 	sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);  in sdhci_reset()
30 	while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {  in sdhci_reset()
33 			       __func__, (int)mask);  in sdhci_reset()
36 		timeout--;  in sdhci_reset()
44 	if (cmd->resp_type & MMC_RSP_136) {  in sdhci_cmd_done()
47 			cmd->response[i] = sdhci_readl(host,  in sdhci_cmd_done()
48 					SDHCI_RESPONSE + (3-i)*4) << 8;  in sdhci_cmd_done()
50 				cmd->response[i] |= sdhci_readb(host,  in sdhci_cmd_done()
51 						SDHCI_RESPONSE + (3-i)*4-1);  in sdhci_cmd_done()
54 		cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);  in sdhci_cmd_done()
62 	for (i = 0; i < data->blocksize; i += 4) {  in sdhci_transfer_pio()
63 		offs = data->dest + i;  in sdhci_transfer_pio()
64 		if (data->flags == MMC_DATA_READ)  in sdhci_transfer_pio()
74 	unsigned int stat, rdy, mask, timeout, block = 0;  in sdhci_transfer_data()  local
85 	mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;  in sdhci_transfer_data()
91 			return -EIO;  in sdhci_transfer_data()
94 			if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))  in sdhci_transfer_data()
98 			data->dest += data->blocksize;  in sdhci_transfer_data()
99 			if (++block >= data->blocks) {  in sdhci_transfer_data()
111 			start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);  in sdhci_transfer_data()
116 		if (timeout-- > 0)  in sdhci_transfer_data()
120 			return -ETIMEDOUT;  in sdhci_transfer_data()
148 	struct sdhci_host *host = mmc->priv;
152 	u32 mask, flags, mode;  local
154 	int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
157 	/* Timeout unit - ms */
160 	mask = SDHCI_CMD_INHIBIT;
163 		mask |= SDHCI_DATA_INHIBIT;
167 	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
168 		mask &= ~SDHCI_DATA_INHIBIT;
170 	while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
190 	mask = SDHCI_INT_RESPONSE;
191 	if (!(cmd->resp_type & MMC_RSP_PRESENT))
193 	else if (cmd->resp_type & MMC_RSP_136)
195 	else if (cmd->resp_type & MMC_RSP_BUSY) {
198 			mask |= SDHCI_INT_DATA_END;
202 	if (cmd->resp_type & MMC_RSP_CRC)
204 	if (cmd->resp_type & MMC_RSP_OPCODE)
209 	if (cmd->cmdidx == MMC_SEND_TUNING_BLOCK ||
210 	    cmd->cmdidx == MMC_SEND_TUNING_BLOCK_HS200) {
211 		mask &= ~SDHCI_INT_RESPONSE;
212 		mask |= SDHCI_INT_DATA_AVAIL;
220 		trans_bytes = data->blocks * data->blocksize;
221 		if (data->blocks > 1)
224 		if (data->flags == MMC_DATA_READ)
228 		if (data->flags == MMC_DATA_READ)
229 			start_addr = (unsigned long)data->dest;
231 			start_addr = (unsigned long)data->src;
232 		if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
236 			if (data->flags != MMC_DATA_READ)
237 				memcpy(aligned_buffer, data->src, trans_bytes);
242 		 * Always use this bounce-buffer when
247 		if (data->flags != MMC_DATA_READ)
248 			memcpy(aligned_buffer, data->src, trans_bytes);
255 				data->blocksize),
257 		sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
259 	} else if (cmd->resp_type & MMC_RSP_BUSY) {
263 	sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
270 	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
278 			if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
283 				return -ETIMEDOUT;
286 	} while ((stat & mask) != mask);
288 	if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
290 		sdhci_writel(host, mask, SDHCI_INT_STATUS);
292 		ret = -1;
297 	if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
303 		if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
304 				!is_aligned && (data->flags == MMC_DATA_READ))
305 			memcpy(data->dest, aligned_buffer, trans_bytes);
312 		return -ETIMEDOUT;
314 		return -ECOMM;
333 		timeout--;
351 			return -EBUSY;
354 		timeout--;
366 		if (host->clk_mul) {
368 				if ((host->max_clk / div) <= clock)
377 			div--;
380 			if (host->max_clk <= clock) {
386 					if ((host->max_clk / div) <= clock)
395 			if ((host->max_clk / div) <= clock)
400 	if (host->ops && host->ops->set_clock_ext)
401 		host->ops->set_clock_ext(host, div);
409 	host->clock = clock;
417 	if (power != (unsigned short)-1) {
446 	u32 timing = host->mmc->timing;
485 	struct sdhci_host *host = mmc->priv;
503 	struct sdhci_host *host = mmc->priv;
505 	if (host->ops && host->ops->set_control_reg)
506 		host->ops->set_control_reg(host);
508 	if (mmc->clock != host->clock) {
509 		if (host->ops && host->ops->set_clock)
510 			host->ops->set_clock(host, mmc->clock);
512 			sdhci_set_clock(host, mmc->clock);
517 	if (mmc->bus_width == 8) {
520 				(host->quirks & SDHCI_QUIRK_USE_WIDE8))
524 				(host->quirks & SDHCI_QUIRK_USE_WIDE8))
526 		if (mmc->bus_width == 4)
532 	if (!(mmc->timing == MMC_TIMING_LEGACY) &&
533 	    !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
540 	if ((mmc->timing != MMC_TIMING_LEGACY) &&
541 	    (mmc->timing != MMC_TIMING_MMC_HS) &&
542 	    (mmc->timing != MMC_TIMING_SD_HS))
548 	if (host->ops && host->ops->set_ios_post)
549 		host->ops->set_ios_post(host);
556 	struct sdhci_host *host = mmc->priv;
560 	if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
565 			return -ENOMEM;
569 	sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
571 	if (host->ops && host->ops->get_cd)
572 		host->ops->get_cd(host);
577 	/* Mask all sdhci interrupt sources */
596 	    host->mmc->bus_width == MMC_BUS_WIDTH_8BIT)
610 	return sdhci_send_command(host->mmc->dev, &cmd, NULL);
612 	return sdhci_send_command(host->mmc, &cmd, NULL);
643 	return -ETIMEDOUT;
654 	struct sdhci_host *host = mmc->priv;
664 	switch (mmc->timing) {
667 		return -EINVAL;
670 		 * Periodic re-tuning for HS400 is not expected to be needed, so
675 		return -EINVAL;
696 	struct sdhci_host *host = mmc->priv;
698 	if (host->ops && host->ops->set_enhanced_strobe)
699 		return host->ops->set_enhanced_strobe(host);
701 	return -ENOTSUPP;
724 	u32 caps, caps_1;  local
726 	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
729 	if (!(caps & SDHCI_CAN_DO_SDMA)) {
732 		return -EINVAL;
735 	if (host->quirks & SDHCI_QUIRK_REG32_RW)
736 		host->version =
737 			sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
739 		host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
741 	cfg->name = host->name;
743 	cfg->ops = &sdhci_ops;
749 		host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
753 	if (host->max_clk == 0) {
755 			host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
758 			host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
760 		host->max_clk *= 1000000;
761 		if (host->clk_mul)
762 			host->max_clk *= host->clk_mul;
764 	if (host->max_clk == 0) {
767 		return -EINVAL;
769 	if (f_max && (f_max < host->max_clk))
770 		cfg->f_max = f_max;
772 		cfg->f_max = host->max_clk;
774 		cfg->f_min = f_min;
777 			cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
779 			cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
781 	cfg->voltages = 0;
782 	if (caps & SDHCI_CAN_VDD_330)
783 		cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
784 	if (caps & SDHCI_CAN_VDD_300)
785 		cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
786 	if (caps & SDHCI_CAN_VDD_180)
787 		cfg->voltages |= MMC_VDD_165_195;
789 	if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
790 		cfg->voltages |= host->voltages;
792 	cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
796 		if (!(caps & SDHCI_CAN_DO_8BIT))
797 			cfg->host_caps &= ~MMC_MODE_8BIT;
800 	if (host->host_caps)
801 		cfg->host_caps |= host->host_caps;
803 	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
818 	ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
822 	host->mmc = mmc_create(&host->cfg, host);
823 	if (host->mmc == NULL) {
825 		return -ENOMEM;