drivers/mmc/sdhci-cadence.c

5  * SPDX-License-Identifier:	GPL-2.0+
17 /* HRS - Host Register Set (specific to Cadence) */
26 /* SRS - Slot Register Set (SDHCI-compatible) */
55 	{ "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
56 	{ "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
57 	{ "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
58 	{ "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
59 	{ "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
60 	{ "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
61 	{ "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
62 	{ "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
63 	{ "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
64 	{ "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
65 	{ "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
71 	void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS04;  in sdhci_cdns_write_phy_reg()
118 	return sdhci_bind(dev, &plat->mmc, &plat->cfg);  in sdhci_cdns_bind()
132 		return -EINVAL;  in sdhci_cdns_probe()
134 	plat->hrs_addr = devm_ioremap(dev, base, SZ_1K);  in sdhci_cdns_probe()
135 	if (!plat->hrs_addr)  in sdhci_cdns_probe()
136 		return -ENOMEM;  in sdhci_cdns_probe()
138 	host->name = dev->name;  in sdhci_cdns_probe()
139 	host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE;  in sdhci_cdns_probe()
140 	host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD;  in sdhci_cdns_probe()
142 	ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev));  in sdhci_cdns_probe()
146 	ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);  in sdhci_cdns_probe()
150 	upriv->mmc = &plat->mmc;  in sdhci_cdns_probe()
151 	host->mmc = &plat->mmc;  in sdhci_cdns_probe()
152 	host->mmc->priv = host;  in sdhci_cdns_probe()
158 	{ .compatible = "socionext,uniphier-sd4hc" },
159 	{ .compatible = "cdns,sd4hc" },
164 	.name = "sdhci-cdns",