134 	u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);  in mmc_board_init()
137 	pbias_lite = readl(&t2_base->pbias_lite);  in mmc_board_init()
163 	writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,  in mmc_board_init()
166 	writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,  in mmc_board_init()
171 		writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,  in mmc_board_init()
174 	writel(readl(&prcm_base->fclken1_core) |  in mmc_board_init()
178 	writel(readl(&prcm_base->iclken1_core) |  in mmc_board_init()
196 	writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);  in mmc_init_stream()
200 	while (!(readl(&mmc_base->stat) & CC_MASK)) {  in mmc_init_stream()
211 	while (!(readl(&mmc_base->stat) & CC_MASK)) {  in mmc_init_stream()
217 	writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);  in mmc_init_stream()
231 	writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,  in omap_hsmmc_init_setup()
234 	while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {  in omap_hsmmc_init_setup()
240 	writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);  in omap_hsmmc_init_setup()
242 	while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {  in omap_hsmmc_init_setup()
250 	writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,  in omap_hsmmc_init_setup()
253 	reg_val = readl(&mmc_base->con) & RESERVED_MASK;  in omap_hsmmc_init_setup()
265 	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {  in omap_hsmmc_init_setup()
271 	writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);  in omap_hsmmc_init_setup()
273 	writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);  in omap_hsmmc_init_setup()
312 	if (!(readl(&mmc_base->sysctl) & bit)) {  in mmc_reset_controller_fsm()
314 		while (!(readl(&mmc_base->sysctl) & bit)) {  in mmc_reset_controller_fsm()
321 	while ((readl(&mmc_base->sysctl) & bit) != 0) {  in mmc_reset_controller_fsm()
346 	while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
355 	while (readl(&mmc_base->stat)) {
358 				__func__, readl(&mmc_base->stat));
420 		mmc_stat = readl(&mmc_base->stat);
438 				cmd->response[3] = readl(&mmc_base->rsp10);
439 				cmd->response[2] = readl(&mmc_base->rsp32);
440 				cmd->response[1] = readl(&mmc_base->rsp54);
441 				cmd->response[0] = readl(&mmc_base->rsp76);
444 				cmd->response[0] = readl(&mmc_base->rsp10);
473 			mmc_stat = readl(&mmc_base->stat);
490 			writel(readl(&mmc_base->stat) | BRR_MASK,
493 				*output_buf = readl(&mmc_base->data);
500 			writel(readl(&mmc_base->stat) | BWR_MASK,
504 			writel(readl(&mmc_base->stat) | TC_MASK,
528 			mmc_stat = readl(&mmc_base->stat);
545 			writel(readl(&mmc_base->stat) | BWR_MASK,
555 			writel(readl(&mmc_base->stat) | BRR_MASK,
559 			writel(readl(&mmc_base->stat) | TC_MASK,
586 		writel(readl(&mmc_base->con) | DTW_8_BITMODE,
591 		writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
593 		writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
599 		writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
601 		writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
621 	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
627 	writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);