drivers/mmc/omap_hsmmc.c

83 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
84 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
192 void mmc_init_stream(struct hsmmc *mmc_base)  in mmc_init_stream()  argument
196 	writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);  in mmc_init_stream()
198 	writel(MMC_CMD0, &mmc_base->cmd);  in mmc_init_stream()
200 	while (!(readl(&mmc_base->stat) & CC_MASK)) {  in mmc_init_stream()
206 	writel(CC_MASK, &mmc_base->stat)  in mmc_init_stream()
208 	writel(MMC_CMD0, &mmc_base->cmd)  in mmc_init_stream()
211 	while (!(readl(&mmc_base->stat) & CC_MASK)) {  in mmc_init_stream()
217 	writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);  in mmc_init_stream()
223 	struct hsmmc *mmc_base;  in omap_hsmmc_init_setup()  local
228 	mmc_base = priv->base_addr;  in omap_hsmmc_init_setup()
231 	writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,  in omap_hsmmc_init_setup()
232 		&mmc_base->sysconfig);  in omap_hsmmc_init_setup()
234 	while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {  in omap_hsmmc_init_setup()
240 	writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);  in omap_hsmmc_init_setup()
242 	while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {  in omap_hsmmc_init_setup()
249 	writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);  in omap_hsmmc_init_setup()
250 	writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,  in omap_hsmmc_init_setup()
251 		&mmc_base->capa);  in omap_hsmmc_init_setup()
253 	reg_val = readl(&mmc_base->con) & RESERVED_MASK;  in omap_hsmmc_init_setup()
257 		HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);  in omap_hsmmc_init_setup()
260 	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),  in omap_hsmmc_init_setup()
262 	mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,  in omap_hsmmc_init_setup()
265 	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {  in omap_hsmmc_init_setup()
271 	writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);  in omap_hsmmc_init_setup()
273 	writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);  in omap_hsmmc_init_setup()
277 		&mmc_base->ie);  in omap_hsmmc_init_setup()
279 	mmc_init_stream(mmc_base);  in omap_hsmmc_init_setup()
290 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)  in mmc_reset_controller_fsm()  argument
294 	mmc_reg_out(&mmc_base->sysctl, bit, bit);  in mmc_reset_controller_fsm()
312 	if (!(readl(&mmc_base->sysctl) & bit)) {  in mmc_reset_controller_fsm()
314 		while (!(readl(&mmc_base->sysctl) & bit)) {  in mmc_reset_controller_fsm()
321 	while ((readl(&mmc_base->sysctl) & bit) != 0) {  in mmc_reset_controller_fsm()
340 	struct hsmmc *mmc_base;  local
344 	mmc_base = priv->base_addr;
346 	while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
353 	writel(0xFFFFFFFF, &mmc_base->stat);
355 	while (readl(&mmc_base->stat)) {
358 				__func__, readl(&mmc_base->stat));
404 							&mmc_base->blk);
406 			writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
414 	writel(cmd->cmdarg, &mmc_base->arg);
416 	writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
420 		mmc_stat = readl(&mmc_base->stat);
428 		mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
434 		writel(CC_MASK, &mmc_base->stat);
438 				cmd->response[3] = readl(&mmc_base->rsp10);
439 				cmd->response[2] = readl(&mmc_base->rsp32);
440 				cmd->response[1] = readl(&mmc_base->rsp54);
441 				cmd->response[0] = readl(&mmc_base->rsp76);
444 				cmd->response[0] = readl(&mmc_base->rsp10);
449 		mmc_read_data(mmc_base,	data->dest,
452 		mmc_write_data(mmc_base, data->src,
458 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)  argument
473 			mmc_stat = readl(&mmc_base->stat);
482 			mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
490 			writel(readl(&mmc_base->stat) | BRR_MASK,
491 				&mmc_base->stat);
493 				*output_buf = readl(&mmc_base->data);
500 			writel(readl(&mmc_base->stat) | BWR_MASK,
501 				&mmc_base->stat);
504 			writel(readl(&mmc_base->stat) | TC_MASK,
505 				&mmc_base->stat);
512 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,  argument
528 			mmc_stat = readl(&mmc_base->stat);
537 			mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
545 			writel(readl(&mmc_base->stat) | BWR_MASK,
546 					&mmc_base->stat);
548 				writel(*input_buf, &mmc_base->data);
555 			writel(readl(&mmc_base->stat) | BRR_MASK,
556 				&mmc_base->stat);
559 			writel(readl(&mmc_base->stat) | TC_MASK,
560 				&mmc_base->stat);
578 	struct hsmmc *mmc_base;  local
582 	mmc_base = priv->base_addr;
586 		writel(readl(&mmc_base->con) | DTW_8_BITMODE,
587 			&mmc_base->con);
591 		writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
592 			&mmc_base->con);
593 		writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
594 			&mmc_base->hctl);
599 		writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
600 			&mmc_base->con);
601 		writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
602 			&mmc_base->hctl);
614 	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
617 	mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
621 	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
627 	writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);