Lines Matching +full:no +full:- +full:mmc
4 * Sukumar Ghorai <s-ghorai@ti.com>
22 * MA 02111-1307 USA
28 #include <mmc.h>
87 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc) in omap_hsmmc_get_data() argument
90 return dev_get_priv(mmc->dev); in omap_hsmmc_get_data()
92 return (struct omap_hsmmc_data *)mmc->priv; in omap_hsmmc_get_data()
95 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc) in omap_hsmmc_get_cfg() argument
98 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev); in omap_hsmmc_get_cfg()
99 return &plat->cfg; in omap_hsmmc_get_cfg()
101 return &((struct omap_hsmmc_data *)mmc->priv)->cfg; in omap_hsmmc_get_cfg()
112 return -1; in omap_mmc_setup_gpio_in()
126 static unsigned char mmc_board_init(struct mmc *mmc) in mmc_board_init() argument
129 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc); in mmc_board_init()
137 pbias_lite = readl(&t2_base->pbias_lite); in mmc_board_init()
150 writel(pbias_lite, &t2_base->pbias_lite); in mmc_board_init()
154 &t2_base->pbias_lite); in mmc_board_init()
163 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, in mmc_board_init()
164 &t2_base->devconf0); in mmc_board_init()
166 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL, in mmc_board_init()
167 &t2_base->devconf1); in mmc_board_init()
170 if (!(cfg->host_caps & MMC_MODE_HS_52MHz)) in mmc_board_init()
171 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL, in mmc_board_init()
172 &t2_base->ctl_prog_io1); in mmc_board_init()
174 writel(readl(&prcm_base->fclken1_core) | in mmc_board_init()
176 &prcm_base->fclken1_core); in mmc_board_init()
178 writel(readl(&prcm_base->iclken1_core) | in mmc_board_init()
180 &prcm_base->iclken1_core); in mmc_board_init()
185 if (mmc_get_blk_desc(mmc)->devnum == 0) in mmc_board_init()
196 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); in mmc_init_stream()
198 writel(MMC_CMD0, &mmc_base->cmd); in mmc_init_stream()
200 while (!(readl(&mmc_base->stat) & CC_MASK)) { in mmc_init_stream()
201 if (get_timer(0) - start > MAX_RETRY_MS) { in mmc_init_stream()
206 writel(CC_MASK, &mmc_base->stat) in mmc_init_stream()
208 writel(MMC_CMD0, &mmc_base->cmd) in mmc_init_stream()
211 while (!(readl(&mmc_base->stat) & CC_MASK)) { in mmc_init_stream()
212 if (get_timer(0) - start > MAX_RETRY_MS) { in mmc_init_stream()
217 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); in mmc_init_stream()
220 static int omap_hsmmc_init_setup(struct mmc *mmc) in omap_hsmmc_init_setup() argument
222 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); in omap_hsmmc_init_setup()
228 mmc_base = priv->base_addr; in omap_hsmmc_init_setup()
229 mmc_board_init(mmc); in omap_hsmmc_init_setup()
231 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, in omap_hsmmc_init_setup()
232 &mmc_base->sysconfig); in omap_hsmmc_init_setup()
234 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) { in omap_hsmmc_init_setup()
235 if (get_timer(0) - start > MAX_RETRY_MS) { in omap_hsmmc_init_setup()
237 return -ETIMEDOUT; in omap_hsmmc_init_setup()
240 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); in omap_hsmmc_init_setup()
242 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) { in omap_hsmmc_init_setup()
243 if (get_timer(0) - start > MAX_RETRY_MS) { in omap_hsmmc_init_setup()
246 return -ETIMEDOUT; in omap_hsmmc_init_setup()
249 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); in omap_hsmmc_init_setup()
250 writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, in omap_hsmmc_init_setup()
251 &mmc_base->capa); in omap_hsmmc_init_setup()
253 reg_val = readl(&mmc_base->con) & RESERVED_MASK; in omap_hsmmc_init_setup()
257 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); in omap_hsmmc_init_setup()
260 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), in omap_hsmmc_init_setup()
262 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, in omap_hsmmc_init_setup()
265 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { in omap_hsmmc_init_setup()
266 if (get_timer(0) - start > MAX_RETRY_MS) { in omap_hsmmc_init_setup()
268 return -ETIMEDOUT; in omap_hsmmc_init_setup()
271 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); in omap_hsmmc_init_setup()
273 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); in omap_hsmmc_init_setup()
277 &mmc_base->ie); in omap_hsmmc_init_setup()
285 * MMC controller internal finite state machine reset
294 mmc_reg_out(&mmc_base->sysctl, bit, bit); in mmc_reset_controller_fsm()
312 if (!(readl(&mmc_base->sysctl) & bit)) { in mmc_reset_controller_fsm()
314 while (!(readl(&mmc_base->sysctl) & bit)) { in mmc_reset_controller_fsm()
315 if (get_timer(0) - start > MAX_RETRY_MS) in mmc_reset_controller_fsm()
321 while ((readl(&mmc_base->sysctl) & bit) != 0) { in mmc_reset_controller_fsm()
322 if (get_timer(0) - start > MAX_RETRY_MS) { in mmc_reset_controller_fsm()
330 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, argument
333 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
344 mmc_base = priv->base_addr;
346 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
347 if (get_timer(0) - start > MAX_RETRY_MS) {
350 return -ETIMEDOUT;
353 writel(0xFFFFFFFF, &mmc_base->stat);
355 while (readl(&mmc_base->stat)) {
356 if (get_timer(0) - start > MAX_RETRY_MS) {
358 __func__, readl(&mmc_base->stat));
359 return -ETIMEDOUT;
369 * 00 = No Response
375 * retry not supported by mmc.c(core file)
377 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
380 if (!(cmd->resp_type & MMC_RSP_PRESENT))
382 else if (cmd->resp_type & MMC_RSP_136)
384 else if (cmd->resp_type & MMC_RSP_BUSY)
393 if (cmd->resp_type & MMC_RSP_CRC)
395 if (cmd->resp_type & MMC_RSP_OPCODE)
399 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
400 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
402 data->blocksize = 512;
403 writel(data->blocksize | (data->blocks << 16),
404 &mmc_base->blk);
406 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
408 if (data->flags & MMC_DATA_READ)
414 writel(cmd->cmdarg, &mmc_base->arg);
415 udelay(20); /* To fix "No status update" error on eMMC */
416 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
420 mmc_stat = readl(&mmc_base->stat);
421 if (get_timer(0) - start > MAX_RETRY_MS) {
422 printf("%s : timeout: No status update\n", __func__);
423 return -ETIMEDOUT;
429 return -ETIMEDOUT;
431 return -1;
434 writel(CC_MASK, &mmc_base->stat);
435 if (cmd->resp_type & MMC_RSP_PRESENT) {
436 if (cmd->resp_type & MMC_RSP_136) {
438 cmd->response[3] = readl(&mmc_base->rsp10);
439 cmd->response[2] = readl(&mmc_base->rsp32);
440 cmd->response[1] = readl(&mmc_base->rsp54);
441 cmd->response[0] = readl(&mmc_base->rsp76);
444 cmd->response[0] = readl(&mmc_base->rsp10);
448 if (data && (data->flags & MMC_DATA_READ)) {
449 mmc_read_data(mmc_base, data->dest,
450 data->blocksize * data->blocks);
451 } else if (data && (data->flags & MMC_DATA_WRITE)) {
452 mmc_write_data(mmc_base, data->src,
453 data->blocksize * data->blocks);
473 mmc_stat = readl(&mmc_base->stat);
474 if (get_timer(0) - start > MAX_RETRY_MS) {
477 return -ETIMEDOUT;
490 writel(readl(&mmc_base->stat) | BRR_MASK,
491 &mmc_base->stat);
493 *output_buf = readl(&mmc_base->data);
496 size -= (count*4);
500 writel(readl(&mmc_base->stat) | BWR_MASK,
501 &mmc_base->stat);
504 writel(readl(&mmc_base->stat) | TC_MASK,
505 &mmc_base->stat);
528 mmc_stat = readl(&mmc_base->stat);
529 if (get_timer(0) - start > MAX_RETRY_MS) {
532 return -ETIMEDOUT;
545 writel(readl(&mmc_base->stat) | BWR_MASK,
546 &mmc_base->stat);
548 writel(*input_buf, &mmc_base->data);
551 size -= (count*4);
555 writel(readl(&mmc_base->stat) | BRR_MASK,
556 &mmc_base->stat);
559 writel(readl(&mmc_base->stat) | TC_MASK,
560 &mmc_base->stat);
568 static int omap_hsmmc_set_ios(struct mmc *mmc) argument
570 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
576 struct mmc *mmc = upriv->mmc;
582 mmc_base = priv->base_addr;
584 switch (mmc->bus_width) {
586 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
587 &mmc_base->con);
591 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
592 &mmc_base->con);
593 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
594 &mmc_base->hctl);
599 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
600 &mmc_base->con);
601 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
602 &mmc_base->hctl);
608 if (mmc->clock != 0) {
609 dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
610 if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
614 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
617 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
621 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
622 if (get_timer(0) - start > MAX_RETRY_MS) {
624 return -ETIMEDOUT;
627 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
639 value = dm_gpio_get_value(&priv->cd_gpio);
640 /* if no CD return as 1 */
644 if (priv->cd_inverted)
654 value = dm_gpio_get_value(&priv->wp_gpio);
655 /* if no WP return as 0 */
661 static int omap_hsmmc_getcd(struct mmc *mmc) argument
663 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
666 /* if no CD return as 1 */
667 cd_gpio = priv->cd_gpio;
671 /* NOTE: assumes card detect signal is active-low */
675 static int omap_hsmmc_getwp(struct mmc *mmc) argument
677 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
680 /* if no WP return as 0 */
681 wp_gpio = priv->wp_gpio;
685 /* NOTE: assumes write protect signal is active-high */
716 struct mmc *mmc; local
723 return -1;
729 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
733 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
738 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
745 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
747 /* Enable 8-bit interface for eMMC on DRA7XX */
753 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
757 /* on error gpio values are set to -1, which is what we want */
758 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
759 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
762 cfg = &priv->cfg;
764 cfg->name = "OMAP SD/MMC";
765 cfg->ops = &omap_hsmmc_ops;
767 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
768 cfg->host_caps = host_caps_val & ~host_caps_mask;
770 cfg->f_min = 400000;
773 cfg->f_max = f_max;
775 if (cfg->host_caps & MMC_MODE_HS) {
776 if (cfg->host_caps & MMC_MODE_HS_52MHz)
777 cfg->f_max = 52000000;
779 cfg->f_max = 26000000;
781 cfg->f_max = 20000000;
784 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
791 cfg->b_max = 1;
793 mmc = mmc_create(cfg, priv);
794 if (mmc == NULL)
795 return -1;
804 struct mmc_config *cfg = &plat->cfg;
807 const void *fdt = gd->fdt_blob;
811 plat->base_addr = map_physmem(devfdt_get_addr(dev),
813 MAP_NOCACHE) + data->reg_offset;
815 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
816 val = fdtdec_get_int(fdt, node, "bus-width", -1);
818 printf("error: bus-width property missing\n");
819 return -ENOENT;
824 cfg->host_caps |= MMC_MODE_8BIT;
826 cfg->host_caps |= MMC_MODE_4BIT;
829 printf("error: invalid bus-width property\n");
830 return -ENOENT;
833 cfg->f_min = 400000;
834 cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000);
835 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
836 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
839 plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted");
852 return mmc_bind(dev, &plat->mmc, &plat->cfg);
860 struct mmc_config *cfg = &plat->cfg;
861 struct mmc *mmc; local
863 cfg->name = "OMAP SD/MMC";
864 priv->base_addr = plat->base_addr;
866 priv->cd_inverted = plat->cd_inverted;
870 mmc = &plat->mmc;
872 mmc = mmc_create(cfg, priv);
873 if (mmc == NULL)
874 return -1;
878 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
879 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
882 mmc->dev = dev;
883 upriv->mmc = mmc;
885 return omap_hsmmc_init_setup(mmc);
903 .compatible = "ti,omap3-hsmmc",
907 .compatible = "ti,omap4-hsmmc",
911 .compatible = "ti,am33xx-hsmmc",