29 static void mvebu_mmc_write(u32 offs, u32 val)  in mvebu_mmc_write()  function
50 	mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);  in mvebu_mmc_setup_data()
53 		mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->dest & 0xffff);  in mvebu_mmc_setup_data()
54 		mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->dest >> 16);  in mvebu_mmc_setup_data()
56 		mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->src & 0xffff);  in mvebu_mmc_setup_data()
57 		mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->src >> 16);  in mvebu_mmc_setup_data()
60 	mvebu_mmc_write(SDIO_BLK_COUNT, data->blocks);  in mvebu_mmc_setup_data()
61 	mvebu_mmc_write(SDIO_BLK_SIZE, data->blocksize);  in mvebu_mmc_setup_data()
108 	mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);  in mvebu_mmc_send_cmd()
109 	mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);  in mvebu_mmc_send_cmd()
156 	mvebu_mmc_write(SDIO_ARG_LOW, cmd->cmdarg & 0xffff);  in mvebu_mmc_send_cmd()
157 	mvebu_mmc_write(SDIO_ARG_HI, cmd->cmdarg >> 16);  in mvebu_mmc_send_cmd()
160 	mvebu_mmc_write(SDIO_XFER_MODE, xfertype);  in mvebu_mmc_send_cmd()
163 	mvebu_mmc_write(SDIO_CMD, resptype);  in mvebu_mmc_send_cmd()
246 	mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);  in mvebu_mmc_power_up()
247 	mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);  in mvebu_mmc_power_up()
250 	mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);  in mvebu_mmc_power_up()
252 	mvebu_mmc_write(SDIO_XFER_MODE, 0);  in mvebu_mmc_power_up()
255 	mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);  in mvebu_mmc_power_up()
256 	mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);  in mvebu_mmc_power_up()
259 	mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);  in mvebu_mmc_power_up()
260 	mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);  in mvebu_mmc_power_up()
269 		mvebu_mmc_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);  in mvebu_mmc_set_clk()
270 		mvebu_mmc_write(SDIO_CLK_DIV, MVEBU_MMC_BASE_DIV_MAX);  in mvebu_mmc_set_clk()
275 		mvebu_mmc_write(SDIO_CLK_DIV, m & MVEBU_MMC_BASE_DIV_MAX);  in mvebu_mmc_set_clk()
316 	mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);  in mvebu_mmc_set_bus()
337 		mvebu_mmc_write(WINDOW_CTRL(i), 0);  in mvebu_window_setup()
338 		mvebu_mmc_write(WINDOW_BASE(i), 0);  in mvebu_window_setup()
366 			mvebu_mmc_write(WINDOW_CTRL(i),  in mvebu_window_setup()
372 			mvebu_mmc_write(WINDOW_CTRL(i), MVCPU_WIN_DISABLE);  in mvebu_window_setup()
374 		mvebu_mmc_write(WINDOW_BASE(i), base);  in mvebu_window_setup()
387 	mvebu_mmc_write(SDIO_HOST_CTRL,  in mvebu_mmc_initialize()
394 	mvebu_mmc_write(SDIO_CLK_CTRL, 0);  in mvebu_mmc_initialize()
397 	mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);  in mvebu_mmc_initialize()
398 	mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);  in mvebu_mmc_initialize()
401 	mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);  in mvebu_mmc_initialize()
402 	mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);  in mvebu_mmc_initialize()
407 	mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);  in mvebu_mmc_initialize()