14 #define gicd_writel(v, offset)	writel(v, (void *)GICD_BASE + (offset))  macro
69 	gicd_writel(val, GICD_CTLR);  in int_enable_distributor()
78 	gicd_writel(val, GICD_CTLR);  in int_disable_distributor()
124 		gicd_writel(val, GICD_ICFGR + IRQ_REG_X16(irq));  in gic_irq_set_trigger()
128 		gicd_writel(val, GICD_ICFGR + IRQ_REG_X16(irq));  in gic_irq_set_trigger()
146 	gicd_writel(val, GICD_ISENABLERn + IRQ_REG_X32(irq));  in gic_irq_enable()
153 	gicd_writel(val, GICD_ITARGETSRn + IRQ_REG_X4(irq));  in gic_irq_enable()
161 	gicd_writel(val, GICD_ISENABLERn + IRQ_REG_X32(irq));  in gic_irq_enable()
173 	gicd_writel(1 << IRQ_REG_X32_OFFSET(irq),  in gic_irq_disable()
301 	gicd_writel(0, GICD_CTLR);  in gic_irq_resume()
306 		gicd_writel(0xffffffff,  in gic_irq_resume()
310 		gicd_writel(gicd_save.icfgr[i++],  in gic_irq_resume()
314 		gicd_writel(gicd_save.itargetsr[i++],  in gic_irq_resume()
318 		gicd_writel(gicd_save.ipriorityr[i++],  in gic_irq_resume()
322 		gicd_writel(gicd_save.igroupr[i++],  in gic_irq_resume()
326 		gicd_writel(gicd_save.isenabler[i++],  in gic_irq_resume()
330 		gicd_writel(gicd_save.ispendr[i++],  in gic_irq_resume()
343 	gicd_writel(gicd_save.ctlr, GICD_CTLR);  in gic_irq_resume()
375 	gicd_writel(0, GICD_CTLR);  in gic_irq_init()
378 	gicd_writel(0xffffffff, GICD_ICENABLERn + 0);  in gic_irq_init()
379 	gicd_writel(0xffffffff, GICD_ICENABLERn + 4);  in gic_irq_init()
380 	gicd_writel(0xffffffff, GICD_ICENABLERn + 8);  in gic_irq_init()
381 	gicd_writel(0xffffffff, GICD_ICENABLERn + 12);  in gic_irq_init()
385 	gicd_writel(val, GICD_ICFGR + 12);  in gic_irq_init()