10 #include "irq-internal.h"
20 #define IRQ_REG_X4(irq)		(4 * ((irq) / 4))  argument
21 #define IRQ_REG_X16(irq)	(4 * ((irq) / 16))  argument
22 #define IRQ_REG_X32(irq)	(4 * ((irq) / 32))  argument
23 #define IRQ_REG_X4_OFFSET(irq)	((irq) % 4)  argument
24 #define IRQ_REG_X16_OFFSET(irq)	((irq) % 16)  argument
25 #define IRQ_REG_X32_OFFSET(irq)	((irq) % 32)  argument
117 static int gic_irq_set_trigger(int irq, eINT_TRIG trig)  in gic_irq_set_trigger()  argument
122 		val = gicd_readl(GICD_ICFGR + IRQ_REG_X16(irq));  in gic_irq_set_trigger()
123 		val &= ~(1 << (2 * IRQ_REG_X16_OFFSET(irq) + 1));  in gic_irq_set_trigger()
124 		gicd_writel(val, GICD_ICFGR + IRQ_REG_X16(irq));  in gic_irq_set_trigger()
126 		val = gicd_readl(GICD_ICFGR + IRQ_REG_X16(irq));  in gic_irq_set_trigger()
127 		val |= (1 << (2 * IRQ_REG_X16_OFFSET(irq) + 1));  in gic_irq_set_trigger()
128 		gicd_writel(val, GICD_ICFGR + IRQ_REG_X16(irq));  in gic_irq_set_trigger()
134 static int gic_irq_enable(int irq)  in gic_irq_enable()  argument
138 	u32 shift = (irq % 4) * 8;  in gic_irq_enable()
140 	if (irq >= PLATFORM_GIC_MAX_IRQ)  in gic_irq_enable()
144 	val = gicd_readl(GICD_ISENABLERn + IRQ_REG_X32(irq));  in gic_irq_enable()
145 	val |= 1 << IRQ_REG_X32_OFFSET(irq);  in gic_irq_enable()
146 	gicd_writel(val, GICD_ISENABLERn + IRQ_REG_X32(irq));  in gic_irq_enable()
150 	val = gicd_readl(GICD_ITARGETSRn + IRQ_REG_X4(irq));  in gic_irq_enable()
153 	gicd_writel(val, GICD_ITARGETSRn + IRQ_REG_X4(irq));  in gic_irq_enable()
159 	val = gicd_readl(GICD_ISENABLERn + IRQ_REG_X32(irq));  in gic_irq_enable()
160 	val |= 1 << IRQ_REG_X32_OFFSET(irq);  in gic_irq_enable()
161 	gicd_writel(val, GICD_ISENABLERn + IRQ_REG_X32(irq));  in gic_irq_enable()
165 	gicd_writeq(affinity_val, GICD_IROUTERn + (irq << 3));  in gic_irq_enable()
171 static int gic_irq_disable(int irq)  in gic_irq_disable()  argument
173 	gicd_writel(1 << IRQ_REG_X32_OFFSET(irq),  in gic_irq_disable()
174 		    GICD_ICENABLERn + IRQ_REG_X32(irq));  in gic_irq_disable()
180  * irq_set_type - set the irq trigger type for an irq
182  * @irq: irq number
183  * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see asm/arch/irq.h
185 static int gic_irq_set_type(int irq, unsigned int type)  in gic_irq_set_type()  argument
202 	gic_irq_set_trigger(irq, int_type);  in gic_irq_set_type()
207 static void gic_irq_eoi(int irq)  in gic_irq_eoi()  argument
210 	gicc_writel(irq, GICC_EOIR);  in gic_irq_eoi()
212 	asm volatile("msr " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" ((u64)irq));  in gic_irq_eoi()
213 	asm volatile("msr " __stringify(ICC_DIR_EL1) ", %0" : : "r" ((u64)irq));  in gic_irq_eoi()
232 	int irq_nr, i, irq;  in gic_irq_suspend()  local
236 	/* irq nr */  in gic_irq_suspend()
255 	for (i = 0, irq = 0; irq < irq_nr; irq += 16)  in gic_irq_suspend()
257 			gicd_readl(GICD_ICFGR + IRQ_REG_X16(irq));  in gic_irq_suspend()
259 	for (i = 0, irq = 0; irq < irq_nr; irq += 4)  in gic_irq_suspend()
261 			gicd_readl(GICD_ITARGETSRn + IRQ_REG_X4(irq));  in gic_irq_suspend()
263 	for (i = 0, irq = 0; irq < irq_nr; irq += 4)  in gic_irq_suspend()
265 			gicd_readl(GICD_IPRIORITYRn + IRQ_REG_X4(irq));  in gic_irq_suspend()
267 	for (i = 0, irq = 0; irq < irq_nr; irq += 32)  in gic_irq_suspend()
269 			gicd_readl(GICD_IGROUPRn + IRQ_REG_X32(irq));  in gic_irq_suspend()
271 	for (i = 0, irq = 0; irq < irq_nr; irq += 32)  in gic_irq_suspend()
273 			gicd_readl(GICD_ISPENDRn + IRQ_REG_X32(irq));  in gic_irq_suspend()
275 	for (i = 0, irq = 0; irq < irq_nr; irq += 32)  in gic_irq_suspend()
277 			gicd_readl(GICD_ISENABLERn + IRQ_REG_X32(irq));  in gic_irq_suspend()
286 	int irq_nr, i, irq;  in gic_irq_resume()  local
305 	for (i = 0, irq = 0; irq < irq_nr; irq += 32)  in gic_irq_resume()
307 			    GICD_ICENABLERn + IRQ_REG_X32(irq));  in gic_irq_resume()
309 	for (i = 0, irq = 0; irq < irq_nr; irq += 16)  in gic_irq_resume()
311 			    GICD_ICFGR + IRQ_REG_X16(irq));  in gic_irq_resume()
313 	for (i = 0, irq = 0; irq < irq_nr; irq += 4)  in gic_irq_resume()
315 			    GICD_ITARGETSRn + IRQ_REG_X4(irq));  in gic_irq_resume()
317 	for (i = 0, irq = 0; irq < irq_nr; irq += 4)  in gic_irq_resume()
319 			    GICD_IPRIORITYRn + IRQ_REG_X4(irq));  in gic_irq_resume()
321 	for (i = 0, irq = 0; irq < irq_nr; irq += 32)  in gic_irq_resume()
323 			    GICD_IGROUPRn + IRQ_REG_X32(irq));  in gic_irq_resume()
325 	for (i = 0, irq = 0; irq < irq_nr; irq += 32)  in gic_irq_resume()
327 			    GICD_ISENABLERn + IRQ_REG_X32(irq));  in gic_irq_resume()
329 	for (i = 0, irq = 0; irq < irq_nr; irq += 32)  in gic_irq_resume()
331 			    GICD_ISPENDRn + IRQ_REG_X32(irq));  in gic_irq_resume()
398 	.name		= "gic-irq-chip",