Lines Matching +full:i2c +full:- +full:controller +full:- +full:id
3 * Copyright (c) 2010-2011 NVIDIA Corporation
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <i2c.h>
21 #include <asm/arch-tegra/tegra_i2c.h>
31 /* Information about i2c controller */
33 int id; member
50 if (i2c_bus->type == TYPE_DVC) { in set_packet_mode()
51 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs; in set_packet_mode()
53 writel(config, &dvc->cnfg); in set_packet_mode()
55 writel(config, &i2c_bus->regs->cnfg); in set_packet_mode()
60 setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK); in set_packet_mode()
66 /* Reset I2C controller. */ in i2c_reset_controller()
67 reset_assert(&i2c_bus->reset_ctl); in i2c_reset_controller()
69 reset_deassert(&i2c_bus->reset_ctl); in i2c_reset_controller()
72 /* re-program config register to packet mode */ in i2c_reset_controller()
80 ret = reset_assert(&i2c_bus->reset_ctl); in i2c_init_clock()
83 ret = clk_enable(&i2c_bus->clk); in i2c_init_clock()
86 ret = clk_set_rate(&i2c_bus->clk, rate); in i2c_init_clock()
89 ret = reset_deassert(&i2c_bus->reset_ctl); in i2c_init_clock()
98 if (!i2c_bus->speed) in i2c_init_controller()
100 debug("%s: speed=%d\n", __func__, i2c_bus->speed); in i2c_init_controller()
102 * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8 in i2c_init_controller()
106 i2c_init_clock(i2c_bus, i2c_bus->speed * 2 * 8); in i2c_init_controller()
108 if (i2c_bus->type == TYPE_114) { in i2c_init_controller()
110 * T114 I2C went to a single clock source for standard/fast and in i2c_init_controller()
112 * SCL = CLK_SOURCE.I2C / in i2c_init_controller()
114 * I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1). in i2c_init_controller()
117 * because if we read the clk_div reg before the controller in i2c_init_controller()
120 int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16; in i2c_init_controller()
122 (clk_div_stdfst_mode + 1) * i2c_bus->speed * 2; in i2c_init_controller()
129 /* Reset I2C controller. */ in i2c_init_controller()
132 /* Configure I2C controller. */ in i2c_init_controller()
133 if (i2c_bus->type == TYPE_DVC) { /* only for DVC I2C */ in i2c_init_controller()
134 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs; in i2c_init_controller()
136 setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK); in i2c_init_controller()
140 funcmux_select(i2c_bus->clk.id, i2c_bus->pinmux_config); in i2c_init_controller()
152 /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */ in send_packet_headers()
155 data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT; in send_packet_headers()
156 writel(data, &i2c_bus->control->tx_fifo); in send_packet_headers()
160 data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT; in send_packet_headers()
161 writel(data, &i2c_bus->control->tx_fifo); in send_packet_headers()
165 data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT; in send_packet_headers()
168 if (!(trans->flags & I2C_IS_WRITE)) in send_packet_headers()
173 /* Write I2C specific header */ in send_packet_headers()
174 writel(data, &i2c_bus->control->tx_fifo); in send_packet_headers()
184 count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK) in wait_for_tx_fifo_empty()
189 timeout_us -= 10; in wait_for_tx_fifo_empty()
201 count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK) in wait_for_rx_fifo_notempty()
206 timeout_us -= 10; in wait_for_rx_fifo_notempty()
218 int_status = readl(&control->int_status); in wait_for_transfer_complete()
220 return -int_status; in wait_for_transfer_complete()
222 return -int_status; in wait_for_transfer_complete()
227 timeout_us -= 10; in wait_for_transfer_complete()
230 return -1; in wait_for_transfer_complete()
236 struct i2c_control *control = i2c_bus->control; in send_recv_packets()
243 int is_write = trans->flags & I2C_IS_WRITE; in send_recv_packets()
246 int_status = readl(&control->int_status); in send_recv_packets()
247 writel(int_status, &control->int_status); in send_recv_packets()
250 trans->flags & I2C_USE_REPEATED_START); in send_recv_packets()
252 words = DIV_ROUND_UP(trans->num_bytes, 4); in send_recv_packets()
253 last_bytes = trans->num_bytes & 3; in send_recv_packets()
254 dptr = trans->buf; in send_recv_packets()
269 writel(local, &control->tx_fifo); in send_recv_packets()
272 error = -1; in send_recv_packets()
277 error = -1; in send_recv_packets()
284 local = readl(&control->rx_fifo); in send_recv_packets()
293 words--; in send_recv_packets()
298 error = -1; in send_recv_packets()
303 /* error, reset the controller. */ in send_recv_packets()
353 i2c_bus->speed = speed; in tegra_i2c_set_bus_speed()
365 i2c_bus->id = dev->seq; in tegra_i2c_probe()
366 i2c_bus->type = dev_get_driver_data(dev); in tegra_i2c_probe()
367 i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev); in tegra_i2c_probe()
368 if ((ulong)i2c_bus->regs == FDT_ADDR_T_NONE) { in tegra_i2c_probe()
370 return -EINVAL; in tegra_i2c_probe()
373 ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl); in tegra_i2c_probe()
378 ret = clk_get_by_name(dev, "div-clk", &i2c_bus->clk); in tegra_i2c_probe()
389 i2c_bus->pinmux_config = FUNCMUX_DEFAULT; in tegra_i2c_probe()
397 * if (i2c_bus->clk.id == PERIPH_ID_I2C2) in tegra_i2c_probe()
398 * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA; in tegra_i2c_probe()
404 i2c_bus->control = in tegra_i2c_probe()
405 &((struct dvc_ctlr *)i2c_bus->regs)->control; in tegra_i2c_probe()
407 i2c_bus->control = &i2c_bus->regs->control; in tegra_i2c_probe()
410 debug("%s: controller bus %d at %p, speed %d: ", in tegra_i2c_probe()
411 is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs, i2c_bus->speed); in tegra_i2c_probe()
416 /* i2c write version without the register address */
429 /* Shift 7-bit address over for lower-level i2c functions */ in i2c_write_data()
438 /* i2c read version without the register address */
445 /* Shift 7-bit address over for lower-level i2c functions */ in i2c_read_data()
469 /* Shift 7-bit address over for lower-level i2c functions */ in tegra_i2c_probe_chip()
483 for (; nmsgs > 0; nmsgs--, msg++) { in tegra_i2c_xfer()
486 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); in tegra_i2c_xfer()
487 if (msg->flags & I2C_M_RD) { in tegra_i2c_xfer()
488 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf, in tegra_i2c_xfer()
489 msg->len); in tegra_i2c_xfer()
491 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf, in tegra_i2c_xfer()
492 msg->len, next_is_read); in tegra_i2c_xfer()
496 return -EREMOTEIO; in tegra_i2c_xfer()
516 return -ENODEV; in tegra_i2c_get_dvc_bus()
526 { .compatible = "nvidia,tegra114-i2c", .data = TYPE_114 },
527 { .compatible = "nvidia,tegra20-i2c", .data = TYPE_STD },
528 { .compatible = "nvidia,tegra20-i2c-dvc", .data = TYPE_DVC },
534 .id = UCLASS_I2C,