Lines Matching +full:i2c +full:- +full:fast +full:- +full:mode
2 * Basic I2C functions
17 * Rewritten to fit into the current U-Boot framework
19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
21 * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions
26 * - Rewritten i2c_read to operate correctly with all types of chips
27 * (old function could not read consistent data from some I2C slaves).
28 * - Optimized i2c_write.
29 * - New i2c_probe, performs write access vs read. The old probe could
31 * - The read/write/probe functions try to identify unconfigured bus.
32 * - Status functions now read irqstatus_raw as per TRM guidelines
34 * - Driver now supports up to I2C5 (OMAP5).
37 * - Added support for set_speed
43 #include <i2c.h>
45 #include <asm/arch/i2c.h>
54 /* Absolutely safe for status update at 100 kHz I2C: */
59 struct i2c *regs;
71 * This method is only called for Standard and Fast Mode speeds in omap24_i2c_findpsc()
74 * page 5685, Table 24-7) in omap24_i2c_findpsc()
75 * that the internal I2C clock (after prescaler) should be between in omap24_i2c_findpsc()
76 * 7-12 MHz (at least for Fast Mode (FS)). in omap24_i2c_findpsc()
79 * ./drivers/i2c/busses/i2c-omap.c (omap_i2c_init function). in omap24_i2c_findpsc()
91 prescaler = prescaler - 1; in omap24_i2c_findpsc()
96 /* Fast mode */ in omap24_i2c_findpsc()
98 *pscl = scl - (scl / 3) - I2C_FASTSPEED_SCLL_TRIM; in omap24_i2c_findpsc()
99 *psch = (scl / 3) - I2C_FASTSPEED_SCLH_TRIM; in omap24_i2c_findpsc()
101 /* Standard mode */ in omap24_i2c_findpsc()
102 *pscl = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLL_TRIM; in omap24_i2c_findpsc()
103 *psch = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLH_TRIM; in omap24_i2c_findpsc()
110 return -EINVAL; in omap24_i2c_findpsc()
119 static int wait_for_bb(struct i2c *i2c_base, int waitdelay)
124 writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
126 while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
129 while ((stat = readw(&i2c_base->irqstatus_raw) &
130 I2C_STAT_BB) && timeout--) {
132 writew(stat, &i2c_base->stat);
141 writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
146 * Wait for the I2C controller to complete current action
149 static u16 wait_for_event(struct i2c *i2c_base, int waitdelay)
157 status = readw(&i2c_base->stat);
160 status = readw(&i2c_base->irqstatus_raw);
165 I2C_STAT_AL)) && timeout--);
172 * not been configured for I2C, and/or pull-ups are missing.
174 printf("Check if pads/pull-ups of bus are properly configured\n");
175 writew(0xFFFF, &i2c_base->stat);
182 static void flush_fifo(struct i2c *i2c_base)
191 stat = readw(&i2c_base->stat);
193 readb(&i2c_base->data);
194 writew(I2C_STAT_RRDY, &i2c_base->stat);
201 static int __omap24_i2c_setspeed(struct i2c *i2c_base, uint speed,
211 psc -= 1;
213 printf("Error : I2C unsupported prescaler %d\n", psc);
214 return -1;
217 /* For first phase of HS mode */
222 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
223 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
226 puts("Error : I2C initializing first phase clock\n");
227 return -1;
230 /* For second phase of HS mode */
233 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
234 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
237 puts("Error : I2C initializing second phase clock\n");
238 return -1;
245 /* Standard and fast speed */
248 puts("Error : I2C initializing clock\n");
249 return -1;
254 writew(0, &i2c_base->con);
255 writew(psc, &i2c_base->psc);
256 writew(scll, &i2c_base->scll);
257 writew(sclh, &i2c_base->sclh);
258 writew(I2C_CON_EN, &i2c_base->con);
259 writew(0xFFFF, &i2c_base->stat); /* clear all pending status */
264 static void omap24_i2c_deblock(struct i2c *i2c_base)
270 /* set test mode ST_EN = 1 */
271 orgsystest = readw(&i2c_base->systest);
275 writew(systest, &i2c_base->systest);
278 writew(systest, &i2c_base->systest);
282 writew(systest, &i2c_base->systest);
289 writew(systest, &i2c_base->systest);
293 writew(systest, &i2c_base->systest);
299 writew(systest, &i2c_base->systest);
302 writew(systest, &i2c_base->systest);
305 /* restore original mode */
306 writew(orgsystest, &i2c_base->systest);
309 static void __omap24_i2c_init(struct i2c *i2c_base, int speed, int slaveadd,
316 if (readw(&i2c_base->con) & I2C_CON_EN) {
317 writew(0, &i2c_base->con);
321 writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
324 writew(I2C_CON_EN, &i2c_base->con);
325 while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
327 puts("ERROR: Timeout in soft-reset\n");
334 printf("ERROR: failed to setup I2C bus-speed!\n");
339 writew(slaveadd, &i2c_base->oa);
347 I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
351 writew(0xFFFF, &i2c_base->stat);
353 /* Handle possible failed I2C state */
364 * write-only (like the config register of dual-port EEPROMs)
366 static int __omap24_i2c_probe(struct i2c *i2c_base, int waitdelay, uchar chip)
371 if (chip == readw(&i2c_base->oa))
379 writew(chip, &i2c_base->sa);
382 I2C_CON_STP, &i2c_base->con);
388 * With current high-level command implementation, notifying
405 writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
408 I2C_CON_STP, &i2c_base->con); /* STP */
412 writew(0xFFFF, &i2c_base->stat);
417 * i2c_read: Function now uses a single I2C read transaction with bulk transfer
418 * of the requested number of bytes (note that the 'i2c md' command
422 * Stop-Start (P-S) shall be used (some I2C chips do require a P-S).
429 static int __omap24_i2c_read(struct i2c *i2c_base, int waitdelay, uchar chip,
436 puts("I2C read: addr len < 0\n");
440 puts("I2C read: data len < 0\n");
444 puts("I2C read: NULL pointer passed\n");
449 printf("I2C read: addr len %d not supported\n", alen);
454 puts("I2C read: address out of range\n");
480 writew(alen, &i2c_base->cnt);
482 writew(chip, &i2c_base->sa);
489 I2C_CON_TRX, &i2c_base->con);
491 /* Stop - Start (P-S) */
493 I2C_CON_TRX, &i2c_base->con);
498 /* Try to identify bus that is not padconf'd for I2C */
513 alen--;
516 &i2c_base->data);
517 writew(I2C_STAT_XRDY, &i2c_base->stat);
521 writew(I2C_STAT_ARDY, &i2c_base->stat);
527 writew(chip, &i2c_base->sa);
529 writew(len, &i2c_base->cnt);
533 &i2c_base->con);
539 * Try to identify bus that is not padconf'd for I2C. This
554 *buffer++ = readb(&i2c_base->data);
555 writew(I2C_STAT_RRDY, &i2c_base->stat);
558 writew(I2C_STAT_ARDY, &i2c_base->stat);
565 writew(0xFFFF, &i2c_base->stat);
570 static int __omap24_i2c_write(struct i2c *i2c_base, int waitdelay, uchar chip,
579 puts("I2C write: addr len < 0\n");
584 puts("I2C write: data len < 0\n");
589 puts("I2C write: NULL pointer passed\n");
594 printf("I2C write: addr len %d not supported\n", alen);
599 printf("I2C write: address 0x%x + 0x%x out of range\n",
625 /* Start address phase - will write regoffset + len bytes data */
626 writew(alen + len, &i2c_base->cnt);
628 writew(chip, &i2c_base->sa);
631 I2C_CON_STP, &i2c_base->con);
636 /* Try to identify bus that is not padconf'd for I2C */
650 alen--;
651 writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data);
652 writew(I2C_STAT_XRDY, &i2c_base->stat);
670 writeb(buffer[i], &i2c_base->data);
671 writew(I2C_STAT_XRDY, &i2c_base->stat);
685 } while (!(status & I2C_STAT_ARDY) && timeout--);
691 writew(0xFFFF, &i2c_base->stat);
697 * The legacy I2C functions. These need to get removed once
700 static struct i2c *omap24_get_base(struct i2c_adapter *adap)
702 switch (adap->hwadapnr) {
704 return (struct i2c *)I2C_BASE1;
707 return (struct i2c *)I2C_BASE2;
711 return (struct i2c *)I2C_BASE3;
715 return (struct i2c *)I2C_BASE4;
719 return (struct i2c *)I2C_BASE5;
725 printf("wrong hwadapnr: %d\n", adap->hwadapnr);
735 struct i2c *i2c_base = omap24_get_base(adap);
737 return __omap24_i2c_read(i2c_base, adap->waitdelay, chip, addr,
745 struct i2c *i2c_base = omap24_get_base(adap);
747 return __omap24_i2c_write(i2c_base, adap->waitdelay, chip, addr,
753 struct i2c *i2c_base = omap24_get_base(adap);
756 ret = __omap24_i2c_setspeed(i2c_base, speed, &adap->waitdelay);
758 pr_err("%s: set i2c speed failed\n", __func__);
762 adap->speed = speed;
769 struct i2c *i2c_base = omap24_get_base(adap);
771 return __omap24_i2c_init(i2c_base, speed, slaveadd, &adap->waitdelay);
776 struct i2c *i2c_base = omap24_get_base(adap);
778 return __omap24_i2c_probe(i2c_base, adap->waitdelay, chip);
849 for (; nmsgs > 0; nmsgs--, msg++) {
850 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
851 if (msg->flags & I2C_M_RD) {
852 ret = __omap24_i2c_read(priv->regs, priv->waitdelay,
853 msg->addr, 0, 0, msg->buf,
854 msg->len);
856 ret = __omap24_i2c_write(priv->regs, priv->waitdelay,
857 msg->addr, 0, 0, msg->buf,
858 msg->len);
862 return -EREMOTEIO;
873 priv->speed = speed;
875 return __omap24_i2c_setspeed(priv->regs, speed, &priv->waitdelay);
883 return __omap24_i2c_probe(priv->regs, priv->waitdelay, chip_addr);
890 __omap24_i2c_init(priv->regs, priv->speed, 0, &priv->waitdelay);
899 priv->regs = map_physmem(devfdt_get_addr(bus), sizeof(void *),
901 priv->speed = CONFIG_SYS_OMAP24_I2C_SPEED;
913 { .compatible = "ti,omap3-i2c" },
914 { .compatible = "ti,omap4-i2c" },