Lines Matching +full:bank +full:- +full:number
6 * Most of code taken from linux kernel driver (linux/drivers/gpio/gpio-zynq.c)
7 * Copyright (C) 2009 - 2014 Xilinx, Inc.
9 * SPDX-License-Identifier: GPL-2.0+
47 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
50 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
53 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
56 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
59 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
62 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
65 /* LSW Mask & Data -WO */
66 #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK)) argument
67 /* MSW Mask & Data -WO */
68 #define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK)) argument
69 /* Data Register-RW */
70 #define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK)) argument
71 /* Direction mode reg-RW */
72 #define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK)) argument
73 /* Output enable reg-RW */
74 #define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK)) argument
75 /* Interrupt mask reg-RO */
76 #define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK)) argument
77 /* Interrupt enable reg-WO */
78 #define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK)) argument
79 /* Interrupt disable reg-WO */
80 #define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK)) argument
81 /* Interrupt status reg-RO */
82 #define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK)) argument
83 /* Interrupt type reg-RW */
84 #define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK)) argument
85 /* Interrupt polarity reg-RW */
86 #define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK)) argument
87 /* Interrupt on any, reg-RW */
88 #define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK)) argument
93 /* Mid pin number of a bank */
105 * struct zynq_platform_data - zynq gpio platform data structure
106 * @label: string to store in gpio->label
107 * @ngpio: max number of gpio pins
108 * @max_bank: maximum number of gpio banks
109 * @bank_min: this array represents bank's min pin
110 * @bank_max: this array represents bank's max pin
153 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
155 * @pin_num: gpio pin number within the device
156 * @bank_num: an output parameter used to return the bank number of the gpio
158 * @bank_pin_num: an output parameter used to return pin number within a bank
161 * Returns the bank number and pin offset within the bank.
169 int bank; in zynq_gpio_get_bank_pin() local
171 for (bank = 0; bank < priv->p_data->max_bank; bank++) { in zynq_gpio_get_bank_pin()
172 if ((pin_num >= priv->p_data->bank_min[bank]) && in zynq_gpio_get_bank_pin()
173 (pin_num <= priv->p_data->bank_max[bank])) { in zynq_gpio_get_bank_pin()
174 *bank_num = bank; in zynq_gpio_get_bank_pin()
175 *bank_pin_num = pin_num - in zynq_gpio_get_bank_pin()
176 priv->p_data->bank_min[bank]; in zynq_gpio_get_bank_pin()
181 if (bank >= priv->p_data->max_bank) { in zynq_gpio_get_bank_pin()
182 printf("Inavlid bank and pin num\n"); in zynq_gpio_get_bank_pin()
192 return (gpio >= 0) && (gpio < priv->p_data->ngpio); in gpio_is_valid()
199 return -1; in check_gpio()
211 return -1; in zynq_gpio_get_value()
215 data = readl(priv->base + in zynq_gpio_get_value()
227 return -1; in zynq_gpio_set_value()
233 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM; in zynq_gpio_set_value()
247 writel(value, priv->base + reg_offset); in zynq_gpio_set_value()
259 return -1; in zynq_gpio_direction_input()
263 /* bank 0 pins 7 and 8 are special and cannot be used as inputs */ in zynq_gpio_direction_input()
265 return -1; in zynq_gpio_direction_input()
268 reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_direction_input()
270 writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_direction_input()
283 return -1; in zynq_gpio_direction_output()
288 reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_direction_output()
290 writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_direction_output()
293 reg = readl(priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); in zynq_gpio_direction_output()
295 writel(reg, priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); in zynq_gpio_direction_output()
309 return -1; in zynq_gpio_get_function()
314 reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_get_function()
331 { .compatible = "xlnx,zynq-gpio-1.0",
333 { .compatible = "xlnx,zynqmp-gpio-1.0",
344 while (of_match->compatible) { in zynq_gpio_getplat_data()
345 ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, in zynq_gpio_getplat_data()
346 of_match->compatible); in zynq_gpio_getplat_data()
348 priv->p_data = in zynq_gpio_getplat_data()
349 (struct zynq_platform_data *)of_match->data; in zynq_gpio_getplat_data()
357 if (!priv->p_data) in zynq_gpio_getplat_data()
368 if (priv->p_data) in zynq_gpio_probe()
369 uc_priv->gpio_count = priv->p_data->ngpio; in zynq_gpio_probe()
378 priv->base = devfdt_get_addr(dev); in zynq_gpio_ofdata_to_platdata()