Lines Matching +full:a +full:- +full:gpio
2 * NVIDIA Tegra20 GPIO handling.
3 * (C) Copyright 2010-2012,2015
6 * SPDX-License-Identifier: GPL-2.0+
22 #include <asm/gpio.h>
23 #include <dm/device-internal.h>
24 #include <dt-bindings/gpio/gpio.h>
36 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
39 /* Information about each port at run-time */
42 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
45 /* Return config of pin 'gpio' as GPIO (1) or SFIO (0) */
46 static int get_config(unsigned gpio) in get_config() argument
49 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; in get_config()
53 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); in get_config()
54 type = (u >> GPIO_BIT(gpio)) & 1; in get_config()
57 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); in get_config()
62 /* Config pin 'gpio' as GPIO or SFIO, based on 'type' */
63 static void set_config(unsigned gpio, int type) in set_config() argument
66 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; in set_config()
70 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); in set_config()
72 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); in set_config()
74 u |= 1 << GPIO_BIT(gpio); in set_config()
76 u &= ~(1 << GPIO_BIT(gpio)); in set_config()
77 writel(u, &bank->gpio_config[GPIO_PORT(gpio)]); in set_config()
80 /* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
81 static int get_direction(unsigned gpio) in get_direction() argument
84 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; in get_direction()
88 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]); in get_direction()
89 dir = (u >> GPIO_BIT(gpio)) & 1; in get_direction()
92 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN"); in get_direction()
97 /* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
98 static void set_direction(unsigned gpio, int output) in set_direction() argument
101 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; in set_direction()
105 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN"); in set_direction()
107 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]); in set_direction()
109 u |= 1 << GPIO_BIT(gpio); in set_direction()
111 u &= ~(1 << GPIO_BIT(gpio)); in set_direction()
112 writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]); in set_direction()
115 /* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
116 static void set_level(unsigned gpio, int high) in set_level() argument
119 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; in set_level()
123 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high); in set_level()
125 u = readl(&bank->gpio_out[GPIO_PORT(gpio)]); in set_level()
127 u |= 1 << GPIO_BIT(gpio); in set_level()
129 u &= ~(1 << GPIO_BIT(gpio)); in set_level()
130 writel(u, &bank->gpio_out[GPIO_PORT(gpio)]); in set_level()
137 /* set GPIO pin 'gpio' as an input */
142 /* Configure GPIO direction as input. */ in tegra_gpio_direction_input()
143 set_direction(state->base_gpio + offset, DIRECTION_INPUT); in tegra_gpio_direction_input()
145 /* Enable the pin as a GPIO */ in tegra_gpio_direction_input()
146 set_config(state->base_gpio + offset, 1); in tegra_gpio_direction_input()
151 /* set GPIO pin 'gpio' as an output, with polarity 'value' */
156 int gpio = state->base_gpio + offset; in tegra_gpio_direction_output() local
158 /* Configure GPIO output value. */ in tegra_gpio_direction_output()
159 set_level(gpio, value); in tegra_gpio_direction_output()
161 /* Configure GPIO direction as output. */ in tegra_gpio_direction_output()
162 set_direction(gpio, DIRECTION_OUTPUT); in tegra_gpio_direction_output()
164 /* Enable the pin as a GPIO */ in tegra_gpio_direction_output()
165 set_config(state->base_gpio + offset, 1); in tegra_gpio_direction_output()
170 /* read GPIO IN value of pin 'gpio' */
174 int gpio = state->base_gpio + offset; in tegra_gpio_get_value() local
178 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); in tegra_gpio_get_value()
180 if (get_direction(gpio) == DIRECTION_INPUT) in tegra_gpio_get_value()
181 val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]); in tegra_gpio_get_value()
183 val = readl(&state->bank->gpio_out[GPIO_PORT(gpio)]); in tegra_gpio_get_value()
185 return (val >> GPIO_BIT(gpio)) & 1; in tegra_gpio_get_value()
188 /* write GPIO OUT value to pin 'gpio' */
192 int gpio = state->base_gpio + offset; in tegra_gpio_set_value() local
195 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value); in tegra_gpio_set_value()
197 /* Configure GPIO output value. */ in tegra_gpio_set_value()
198 set_level(gpio, value); in tegra_gpio_set_value()
210 set_direction(config[i].gpio, DIRECTION_INPUT); in gpio_config_table()
213 set_level(config[i].gpio, 0); in gpio_config_table()
214 set_direction(config[i].gpio, DIRECTION_OUTPUT); in gpio_config_table()
217 set_level(config[i].gpio, 1); in gpio_config_table()
218 set_direction(config[i].gpio, DIRECTION_OUTPUT); in gpio_config_table()
221 set_config(config[i].gpio, CONFIG_GPIO); in gpio_config_table()
228 int gpio = state->base_gpio + offset; in tegra_gpio_get_function() local
230 if (!get_config(gpio)) in tegra_gpio_get_function()
232 else if (get_direction(gpio)) in tegra_gpio_get_function()
241 int gpio, port, ret; in tegra_gpio_xlate() local
243 gpio = args->args[0]; in tegra_gpio_xlate()
244 port = gpio / TEGRA_GPIOS_PER_PORT; in tegra_gpio_xlate()
245 ret = device_get_child(dev, port, &desc->dev); in tegra_gpio_xlate()
248 desc->offset = gpio % TEGRA_GPIOS_PER_PORT; in tegra_gpio_xlate()
249 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0; in tegra_gpio_xlate()
264 * Returns the name of a GPIO port
266 * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ...
268 * @base_port: Base port number (0, 1..n-1)
278 *s++ = 'A' + (base_port % 26); in gpio_port_name()
288 { .compatible = "nvidia,tegra30-gpio" },
289 { .compatible = "nvidia,tegra20-gpio" },
296 struct tegra_port_info *priv = dev->priv; in gpio_tegra_probe()
297 struct tegra_gpio_platdata *plat = dev->platdata; in gpio_tegra_probe()
303 priv->bank = plat->bank; in gpio_tegra_probe()
304 priv->base_gpio = plat->base_gpio; in gpio_tegra_probe()
306 uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT; in gpio_tegra_probe()
307 uc_priv->bank_name = plat->port_name; in gpio_tegra_probe()
313 * We have a top-level GPIO device with no actual GPIOs. It has a child
318 struct tegra_gpio_platdata *plat = parent->platdata; in gpio_tegra_bind()
324 /* If this is a child device, there is nothing to do here */ in gpio_tegra_bind()
338 * out the number of GPIO banks in gpio_tegra_bind()
346 return -EINVAL; in gpio_tegra_bind()
359 return -ENOMEM; in gpio_tegra_bind()
360 plat->bank = &ctlr->gpio_bank[bank]; in gpio_tegra_bind()
362 plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port; in gpio_tegra_bind()
363 plat->port_name = gpio_port_name(base_port); in gpio_tegra_bind()
365 ret = device_bind(parent, parent->driver, in gpio_tegra_bind()
366 plat->port_name, plat, -1, &dev); in gpio_tegra_bind()