Lines Matching defs:gpio_reg

20 struct gpio_reg {  struct
21 	u32 gplr;	/* Pin Level Register - 0x0000 */
22 	u32 pad0[2];
23 	u32 gpdr;	/* Pin Direction Register - 0x000C */
24 	u32 pad1[2];
25 	u32 gpsr;	/* Pin Output Set Register - 0x0018 */
26 	u32 pad2[2];
27 	u32 gpcr;	/* Pin Output Clear Register - 0x0024 */
28 	u32 pad3[2];
29 	u32 grer;	/* Rising-Edge Detect Enable Register - 0x0030 */
30 	u32 pad4[2];
31 	u32 gfer;	/* Falling-Edge Detect Enable Register - 0x003C */
32 	u32 pad5[2];
33 	u32 gedr;	/* Edge Detect Status Register - 0x0048 */
34 	u32 pad6[2];
35 	u32 gsdr;	/* Bitwise Set of GPIO Direction Register - 0x0054 */
36 	u32 pad7[2];
37 	u32 gcdr;	/* Bitwise Clear of GPIO Direction Register - 0x0060 */
38 	u32 pad8[2];
39 	u32 gsrer;	/* Bitwise Set of Rising-Edge Detect Enable
41 	u32 pad9[2];
42 	u32 gcrer;	/* Bitwise Clear of Rising-Edge Detect Enable
44 	u32 pad10[2];
45 	u32 gsfer;	/* Bitwise Set of Falling-Edge Detect Enable
47 	u32 pad11[2];
48 	u32 gcfer;	/* Bitwise Clear of Falling-Edge Detect Enable
50 	u32 pad12[2];
51 	u32 apmask;	/* Bitwise Mask of Edge Detect Register - 0x009C */