Lines Matching refs:__func__
94 debug("%s: Let's check bitstream header\n", __func__); in check_header()
110 debug("%s: data swapped - let's swap\n", __func__); in check_header()
113 debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i, in check_header()
116 debug("%s: Bitstream is not recognized\n", __func__); in check_header()
120 debug("%s: Found bitstream header at %x %s swapinng\n", __func__, in check_header()
133 debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]); in check_data()
138 __func__, p, (u32)&buf[p]); in check_data()
169 debug("%s: Error: isr = 0x%08X\n", __func__, in zynq_dma_transfer()
171 debug("%s: Write count = 0x%08X\n", __func__, in zynq_dma_transfer()
173 debug("%s: Read count = 0x%08X\n", __func__, in zynq_dma_transfer()
180 __func__); in zynq_dma_transfer()
186 debug("%s: DMA transfer is done\n", __func__); in zynq_dma_transfer()
216 __func__); in zynq_dma_xfer_init()
230 __func__); in zynq_dma_xfer_init()
242 debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status); in zynq_dma_xfer_init()
254 debug("%s: Status = 0x%08X\n", __func__, status); in zynq_dma_xfer_init()
257 debug("%s: Error: device busy\n", __func__); in zynq_dma_xfer_init()
261 debug("%s: Device ready\n", __func__); in zynq_dma_xfer_init()
266 debug("%s: ISR indicates error\n", __func__); in zynq_dma_xfer_init()
296 __func__); in zynq_align_dma_buffer()
299 printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, in zynq_align_dma_buffer()
310 printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__, in zynq_align_dma_buffer()
336 __func__, diff); in zynq_validate_bitstream()
342 __func__, (u32)buf); in zynq_validate_bitstream()
368 debug("%s: Source = 0x%08X\n", __func__, (u32)buf); in zynq_load()
369 debug("%s: Size = %zu\n", __func__, bsize); in zynq_load()
384 __func__); in zynq_load()
390 debug("%s: FPGA config done\n", __func__); in zynq_load()
464 __func__); in zynq_loadfs()
470 debug("%s: FPGA config done\n", __func__); in zynq_loadfs()