68 	struct mxs_apbh_regs *apbh_regs =  in mxs_dma_read_semaphore()  local
77 	tmp = readl(&apbh_regs->ch[channel].hw_apbh_ch_sema);  in mxs_dma_read_semaphore()
111 	struct mxs_apbh_regs *apbh_regs =  in mxs_dma_enable()  local
145 				&apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);  in mxs_dma_enable()
148 			&apbh_regs->ch[channel].hw_apbh_ch_sema);  in mxs_dma_enable()
155 			&apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);  in mxs_dma_enable()
157 			&apbh_regs->ch[channel].hw_apbh_ch_sema);  in mxs_dma_enable()
159 			&apbh_regs->hw_apbh_ctrl0_clr);  in mxs_dma_enable()
183 	struct mxs_apbh_regs *apbh_regs =  in mxs_dma_disable()  local
197 		&apbh_regs->hw_apbh_ctrl0_set);  in mxs_dma_disable()
212 	struct mxs_apbh_regs *apbh_regs =  in mxs_dma_reset()  local
216 	uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set);  in mxs_dma_reset()
219 	uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set);  in mxs_dma_reset()
239 	struct mxs_apbh_regs *apbh_regs =  in mxs_dma_enable_irq()  local
249 			&apbh_regs->hw_apbh_ctrl1_set);  in mxs_dma_enable_irq()
252 			&apbh_regs->hw_apbh_ctrl1_clr);  in mxs_dma_enable_irq()
265 	struct mxs_apbh_regs *apbh_regs =  in mxs_dma_ack_irq()  local
273 	writel(1 << channel, &apbh_regs->hw_apbh_ctrl1_clr);  in mxs_dma_ack_irq()
274 	writel(1 << channel, &apbh_regs->hw_apbh_ctrl2_clr);  in mxs_dma_ack_irq()
502 	struct mxs_apbh_regs *apbh_regs =  in mxs_dma_wait_complete()  local
510 	if (mxs_wait_mask_set(&apbh_regs->hw_apbh_ctrl1_reg,  in mxs_dma_wait_complete()
555 	struct mxs_apbh_regs *apbh_regs =  in mxs_dma_circ_start()  local
563 		&apbh_regs->ch[chan].hw_apbh_ch_nxtcmdar);  in mxs_dma_circ_start()
564 	writel(1, &apbh_regs->ch[chan].hw_apbh_ch_sema);  in mxs_dma_circ_start()
566 		&apbh_regs->hw_apbh_ctrl0_clr);  in mxs_dma_circ_start()
574 	struct mxs_apbh_regs *apbh_regs =  in mxs_dma_init()  local
577 	mxs_reset_block(&apbh_regs->hw_apbh_ctrl0_reg);  in mxs_dma_init()
581 		&apbh_regs->hw_apbh_ctrl0_set);  in mxs_dma_init()
584 		&apbh_regs->hw_apbh_ctrl0_clr);  in mxs_dma_init()
589 		&apbh_regs->hw_apbh_ctrl0_set);  in mxs_dma_init()
592 		&apbh_regs->hw_apbh_ctrl0_clr);  in mxs_dma_init()