Lines Matching +full:cpu +full:- +full:viewed
10 * SPDX-License-Identifier: GPL-2.0+
20 #include <asm/arch/imx-regs.h>
22 #include <asm/mach-imx/dma.h>
23 #include <asm/mach-imx/regs-apbh.h>
35 return -EINVAL; in mxs_dma_validate_chan()
38 if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) in mxs_dma_validate_chan()
39 return -EINVAL; in mxs_dma_validate_chan()
49 return desc->address + offsetof(struct mxs_dma_desc, cmd); in mxs_dma_cmd_address()
58 * so it must be be viewed as immediately stale.
77 tmp = readl(&apbh_regs->ch[channel].hw_apbh_ch_sema); in mxs_dma_read_semaphore()
124 if (pchan->pending_num == 0) { in mxs_dma_enable()
125 pchan->flags |= MXS_DMA_FLAGS_BUSY; in mxs_dma_enable()
129 pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node); in mxs_dma_enable()
131 return -EFAULT; in mxs_dma_enable()
133 if (pchan->flags & MXS_DMA_FLAGS_BUSY) { in mxs_dma_enable()
134 if (!(pdesc->cmd.data & MXS_DMA_DESC_CHAIN)) in mxs_dma_enable()
142 pdesc = list_entry(pdesc->node.next, in mxs_dma_enable()
145 &apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar); in mxs_dma_enable()
147 writel(pchan->pending_num, in mxs_dma_enable()
148 &apbh_regs->ch[channel].hw_apbh_ch_sema); in mxs_dma_enable()
149 pchan->active_num += pchan->pending_num; in mxs_dma_enable()
150 pchan->pending_num = 0; in mxs_dma_enable()
152 pchan->active_num += pchan->pending_num; in mxs_dma_enable()
153 pchan->pending_num = 0; in mxs_dma_enable()
155 &apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar); in mxs_dma_enable()
156 writel(pchan->active_num, in mxs_dma_enable()
157 &apbh_regs->ch[channel].hw_apbh_ch_sema); in mxs_dma_enable()
159 &apbh_regs->hw_apbh_ctrl0_clr); in mxs_dma_enable()
162 pchan->flags |= MXS_DMA_FLAGS_BUSY; in mxs_dma_enable()
193 if (!(pchan->flags & MXS_DMA_FLAGS_BUSY)) in mxs_dma_disable()
194 return -EINVAL; in mxs_dma_disable()
197 &apbh_regs->hw_apbh_ctrl0_set); in mxs_dma_disable()
199 pchan->flags &= ~MXS_DMA_FLAGS_BUSY; in mxs_dma_disable()
200 pchan->active_num = 0; in mxs_dma_disable()
201 pchan->pending_num = 0; in mxs_dma_disable()
202 list_splice_init(&pchan->active, &pchan->done); in mxs_dma_disable()
216 uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set); in mxs_dma_reset()
219 uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set); in mxs_dma_reset()
235 * This function enables the given DMA channel to interrupt the CPU.
249 &apbh_regs->hw_apbh_ctrl1_set); in mxs_dma_enable_irq()
252 &apbh_regs->hw_apbh_ctrl1_clr); in mxs_dma_enable_irq()
273 writel(1 << channel, &apbh_regs->hw_apbh_ctrl1_clr); in mxs_dma_ack_irq()
274 writel(1 << channel, &apbh_regs->hw_apbh_ctrl2_clr); in mxs_dma_ack_irq()
287 return -EINVAL; in mxs_dma_request()
290 if ((pchan->flags & MXS_DMA_FLAGS_VALID) != MXS_DMA_FLAGS_VALID) in mxs_dma_request()
291 return -ENODEV; in mxs_dma_request()
293 if (pchan->flags & MXS_DMA_FLAGS_ALLOCATED) in mxs_dma_request()
294 return -EBUSY; in mxs_dma_request()
296 pchan->flags |= MXS_DMA_FLAGS_ALLOCATED; in mxs_dma_request()
297 pchan->active_num = 0; in mxs_dma_request()
298 pchan->pending_num = 0; in mxs_dma_request()
300 INIT_LIST_HEAD(&pchan->active); in mxs_dma_request()
301 INIT_LIST_HEAD(&pchan->done); in mxs_dma_request()
325 if (pchan->flags & MXS_DMA_FLAGS_BUSY) in mxs_dma_release()
326 return -EBUSY; in mxs_dma_release()
328 pchan->dev = 0; in mxs_dma_release()
329 pchan->active_num = 0; in mxs_dma_release()
330 pchan->pending_num = 0; in mxs_dma_release()
331 pchan->flags &= ~MXS_DMA_FLAGS_ALLOCATED; in mxs_dma_release()
351 pdesc->address = (dma_addr_t)pdesc; in mxs_dma_desc_alloc()
418 pdesc->cmd.next = mxs_dma_cmd_address(pdesc); in mxs_dma_desc_append()
419 pdesc->flags |= MXS_DMA_DESC_FIRST | MXS_DMA_DESC_LAST; in mxs_dma_desc_append()
421 if (!list_empty(&pchan->active)) { in mxs_dma_desc_append()
422 last = list_entry(pchan->active.prev, struct mxs_dma_desc, in mxs_dma_desc_append()
425 pdesc->flags &= ~MXS_DMA_DESC_FIRST; in mxs_dma_desc_append()
426 last->flags &= ~MXS_DMA_DESC_LAST; in mxs_dma_desc_append()
428 last->cmd.next = mxs_dma_cmd_address(pdesc); in mxs_dma_desc_append()
429 last->cmd.data |= MXS_DMA_DESC_CHAIN; in mxs_dma_desc_append()
433 pdesc->flags |= MXS_DMA_DESC_READY; in mxs_dma_desc_append()
434 if (pdesc->flags & MXS_DMA_DESC_FIRST) in mxs_dma_desc_append()
435 pchan->pending_num++; in mxs_dma_desc_append()
436 list_add_tail(&pdesc->node, &pchan->active); in mxs_dma_desc_append()
447 * in a non-NULL list head to get the descriptors moved to your list. Pass NULL
472 if (sem == pchan->active_num) in mxs_dma_finish()
475 list_for_each_safe(p, q, &pchan->active) { in mxs_dma_finish()
476 if ((pchan->active_num) <= sem) in mxs_dma_finish()
480 pdesc->flags &= ~MXS_DMA_DESC_READY; in mxs_dma_finish()
485 list_move_tail(p, &pchan->done); in mxs_dma_finish()
487 if (pdesc->flags & MXS_DMA_DESC_LAST) in mxs_dma_finish()
488 pchan->active_num--; in mxs_dma_finish()
492 pchan->flags &= ~MXS_DMA_FLAGS_BUSY; in mxs_dma_finish()
510 if (mxs_wait_mask_set(&apbh_regs->hw_apbh_ctrl1_reg, in mxs_dma_wait_complete()
512 ret = -ETIMEDOUT; in mxs_dma_wait_complete()
550 * for the LCD driver in Smart-LCD mode. It allows
563 &apbh_regs->ch[chan].hw_apbh_ch_nxtcmdar); in mxs_dma_circ_start()
564 writel(1, &apbh_regs->ch[chan].hw_apbh_ch_sema); in mxs_dma_circ_start()
566 &apbh_regs->hw_apbh_ctrl0_clr); in mxs_dma_circ_start()
577 mxs_reset_block(&apbh_regs->hw_apbh_ctrl0_reg); in mxs_dma_init()
581 &apbh_regs->hw_apbh_ctrl0_set); in mxs_dma_init()
584 &apbh_regs->hw_apbh_ctrl0_clr); in mxs_dma_init()
589 &apbh_regs->hw_apbh_ctrl0_set); in mxs_dma_init()
592 &apbh_regs->hw_apbh_ctrl0_clr); in mxs_dma_init()
602 pchan->flags = MXS_DMA_FLAGS_VALID; in mxs_dma_init_channel()