Lines Matching refs:DIV_ROUND_UP
106 hc_delay = max_t(u32, DIV_ROUND_UP(delay, T_CK), 2) - 2; in host_load_cmd()
139 writel(REFCNT_CLK(DIV_ROUND_UP(T_RFI, T_CK_CTRL) - 2) | in ddr2_ctrl_init()
140 REFDLY_CLK(DIV_ROUND_UP(T_RFC_MIN, T_CK_CTRL) - 2) | in ddr2_ctrl_init()
151 wr2rd = max_t(u32, DIV_ROUND_UP(T_WTR, T_CK_CTRL), in ddr2_ctrl_init()
152 DIV_ROUND_UP(T_WTR_TCK, 2)) + WL + BL; in ddr2_ctrl_init()
154 wr2prech = DIV_ROUND_UP(T_WR, T_CK_CTRL) + WL + BL; in ddr2_ctrl_init()
155 rd2prech = max_t(u32, DIV_ROUND_UP(T_RTP, T_CK_CTRL), in ddr2_ctrl_init()
156 DIV_ROUND_UP(T_RTP_TCK, 2)) + BL - 2; in ddr2_ctrl_init()
157 ras2ras = max_t(u32, DIV_ROUND_UP(T_RRD, T_CK_CTRL), in ddr2_ctrl_init()
158 DIV_ROUND_UP(T_RRD_TCK, 2)) - 1; in ddr2_ctrl_init()
159 ras2cas = DIV_ROUND_UP(T_RCD, T_CK_CTRL) - 1; in ddr2_ctrl_init()
160 prech2ras = DIV_ROUND_UP(T_RP, T_CK_CTRL) - 1; in ddr2_ctrl_init()
172 (((DIV_ROUND_UP(T_DLLK, 2) - 2) & 0xff) << 8) | in ddr2_ctrl_init()
179 ((DIV_ROUND_UP(T_DLLK, 2) >> 8) << 30)), &ctrl->dlycfg1); in ddr2_ctrl_init()
181 writel((DIV_ROUND_UP(T_RP, T_CK_CTRL) | in ddr2_ctrl_init()
189 writel(((DIV_ROUND_UP(T_RAS_MIN, T_CK_CTRL) - 1) | in ddr2_ctrl_init()
190 ((DIV_ROUND_UP(T_RC, T_CK_CTRL) - 1) << 8) | in ddr2_ctrl_init()
191 ((DIV_ROUND_UP(T_FAW, T_CK_CTRL) - 1) << 16)), in ddr2_ctrl_init()
228 temp = ((DIV_ROUND_UP(T_WR, T_CK) - 1) << 1) | 1; in ddr2_ctrl_init()