Lines Matching refs:dq
97 u32 pup, dq, pups, cur_max_pup, valid_pup, reg; in ddr3_pbs_tx() local
126 for (dq = 0; dq < DQ_NUM; dq++) in ddr3_pbs_tx()
127 skew_sum_array[pup][dq] = 0; in ddr3_pbs_tx()
174 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_tx()
177 (max_pup - 1)][dq] = in ddr3_pbs_tx()
201 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_tx()
207 [dq], CS0, (1 - ecc) * in ddr3_pbs_tx()
254 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_tx()
263 DEBUG_PBS_D(dq, 1); in ddr3_pbs_tx()
267 dq], 2); in ddr3_pbs_tx()
278 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_tx()
280 [dq] += skew_array in ddr3_pbs_tx()
281 [((pup) * DQ_NUM) + dq]; in ddr3_pbs_tx()
303 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_tx()
307 DEBUG_PBS_D(dq, 1); in ddr3_pbs_tx()
309 DEBUG_PBS_D(skew_sum_array[pup][dq] / in ddr3_pbs_tx()
329 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_tx()
330 pattern_skew_array[pup][dq] += in ddr3_pbs_tx()
331 (skew_sum_array[pup][dq] / in ddr3_pbs_tx()
339 for (dq = 0; dq < DQ_NUM; dq++) in ddr3_pbs_tx()
340 skew_array[((pup) * DQ_NUM) + dq] = in ddr3_pbs_tx()
341 pattern_skew_array[pup][dq] / COUNT_PBS_PATTERN; in ddr3_pbs_tx()
354 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_tx()
362 DEBUG_PBS_D(dq, 1); in ddr3_pbs_tx()
364 DEBUG_PBS_D(skew_array[(pup * DQ_NUM) + dq], 2); in ddr3_pbs_tx()
539 u32 pup, dq, pups, cur_max_pup, valid_pup, reg; in ddr3_pbs_rx() local
569 for (dq = 0; dq < DQ_NUM; dq++) in ddr3_pbs_rx()
570 skew_sum_array[pup][dq] = 0; in ddr3_pbs_rx()
616 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_rx()
618 pup + ecc * (max_pup - 1)][dq] = in ddr3_pbs_rx()
641 for (dq = 0; dq < DQ_NUM; dq++) in ddr3_pbs_rx()
647 [dq], CS0, in ddr3_pbs_rx()
711 for (dq = 0; in ddr3_pbs_rx()
712 dq < DQ_NUM; dq++) in ddr3_pbs_rx()
718 [dq], CS0, in ddr3_pbs_rx()
765 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_rx()
774 DEBUG_PBS_FULL_D(dq, 1); in ddr3_pbs_rx()
779 dq], 2); in ddr3_pbs_rx()
790 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_rx()
793 [dq] += in ddr3_pbs_rx()
794 skew_array[((pup) * DQ_NUM) + dq]; in ddr3_pbs_rx()
817 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_rx()
818 pattern_skew_array[pup][dq] += in ddr3_pbs_rx()
819 (skew_sum_array[pup][dq] / in ddr3_pbs_rx()
835 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_rx()
843 DEBUG_PBS_D(dq, 1); in ddr3_pbs_rx()
845 DEBUG_PBS_D(skew_sum_array[pup][dq] / in ddr3_pbs_rx()
855 for (dq = 0; dq < DQ_NUM; dq++) in ddr3_pbs_rx()
856 skew_array[((pup) * DQ_NUM) + dq] = in ddr3_pbs_rx()
857 pattern_skew_array[pup][dq] / COUNT_PBS_PATTERN; in ddr3_pbs_rx()
870 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_rx()
878 DEBUG_PBS_D(dq, 1); in ddr3_pbs_rx()
880 DEBUG_PBS_D(skew_array[(pup * DQ_NUM) + dq], 2); in ddr3_pbs_rx()
1090 u32 dq; in lock_pups() local
1101 for (dq = 0; dq < DQ_NUM; dq++) { in lock_pups()
1102 if (IS_PUP_ACTIVE(unlock_pup_dq_array[dq], pup) == 1) { in lock_pups()
1106 unlock_pup_dq_array[dq] &= ~(1 << pup); in lock_pups()
1107 skew_array[(pup * DQ_NUM) + dq] = pbs_curr_val; in lock_pups()
1115 pbs_dq_mapping[idx][dq], CS0, in lock_pups()
1149 u32 pup, dq; in ddr3_pbs_per_bit() local
1168 for (dq = 0; dq < DQ_NUM; dq++) in ddr3_pbs_per_bit()
1169 cmp_unlock_pup_dq_array[pbs_cmp_retry][dq] = *pcur_pup; in ddr3_pbs_per_bit()
1202 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_per_bit()
1204 if (unlock_pup_dq_array[dq] == 0) { in ddr3_pbs_per_bit()
1206 DEBUG_PBS_FULL_D(dq, 1); in ddr3_pbs_per_bit()
1216 if (IS_PUP_ACTIVE(unlock_pup_dq_array[dq], pup) in ddr3_pbs_per_bit()
1222 PUP_PBS_TX + pbs_dq_mapping[idx][dq], in ddr3_pbs_per_bit()
1226 PUP_PBS_RX + pbs_dq_mapping[idx][dq], in ddr3_pbs_per_bit()
1250 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_per_bit()
1251 if ((IS_PUP_ACTIVE(unlock_pup_dq_array[dq], in ddr3_pbs_per_bit()
1254 [pbs_cmp_retry][dq], in ddr3_pbs_per_bit()
1261 DEBUG_PBS_FULL_D(dq, 1); in ddr3_pbs_per_bit()
1267 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_per_bit()
1268 unlock_pup_dq_array[dq] &= in ddr3_pbs_per_bit()
1269 cmp_unlock_pup_dq_array[pbs_cmp_retry][dq]; in ddr3_pbs_per_bit()
1277 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_per_bit()
1279 pup_locked |= unlock_pup_dq_array[dq]; in ddr3_pbs_per_bit()
1282 sum_pup_fail &= unlock_pup_dq_array[dq]; in ddr3_pbs_per_bit()
1331 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_pbs_per_bit()
1333 (unlock_pup_dq_array[dq], in ddr3_pbs_per_bit()
1335 DEBUG_PBS_FULL_D(dq, 1); in ddr3_pbs_per_bit()
1340 dq] = in ddr3_pbs_per_bit()
1419 u32 pup, phys_pup, dq; in ddr3_set_pbs_results() local
1441 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_set_pbs_results()
1442 if (pbs_min > skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1443 pbs_min = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1445 if (pbs_max < skew_array[(pup * DQ_NUM) + dq]) in ddr3_set_pbs_results()
1446 pbs_max = skew_array[(pup * DQ_NUM) + dq]; in ddr3_set_pbs_results()
1459 for (dq = 0; dq < DQ_NUM; dq++) { in ddr3_set_pbs_results()
1471 DEBUG_PBS_FULL_D(dq, 1); in ddr3_set_pbs_results()
1473 DEBUG_PBS_FULL_D((skew_array[(pup * DQ_NUM) + dq] - in ddr3_set_pbs_results()
1477 idx = (pup * DQ_NUM) + dq; in ddr3_set_pbs_results()
1484 ddr3_write_pup_reg(offs + pbs_dq_mapping[phys_pup][dq], in ddr3_set_pbs_results()