19 	{REG_STATIC_DRAM_DLB_CONTROL, 0x2000005c},
20 	{DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 0x00880000},
21 	{DLB_AGING_REGISTER, 0x0f7f007f},
22 	{DLB_EVICTION_CONTROL_REG, 0x0000129f},
23 	{DLB_EVICTION_TIMERS_REGISTER_REG, 0x00ff0000},
24 	{DLB_BUS_WEIGHTS_DIFF_CS, 0x04030802},
25 	{DLB_BUS_WEIGHTS_DIFF_BG, 0x00000a02},
26 	{DLB_BUS_WEIGHTS_SAME_BG, 0x09000a01},
27 	{DLB_BUS_WEIGHTS_RD_WR, 0x00020005},
28 	{DLB_BUS_WEIGHTS_ATTR_SYS_PRIO, 0x00060f10},
29 	{DLB_MAIN_QUEUE_MAP, 0x00000543},
30 	{DLB_LINE_SPLIT, 0x00000000},
31 	{DLB_USER_COMMAND_REG, 0x00000000},
32 	{0x0, 0x0}
36 	{REG_STATIC_DRAM_DLB_CONTROL, 0x2000005c},
37 	{DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 0x00880000},
38 	{DLB_AGING_REGISTER, 0x0f7f007f},
39 	{DLB_EVICTION_CONTROL_REG, 0x0000129f},
40 	{DLB_EVICTION_TIMERS_REGISTER_REG, 0x00ff0000},
41 	{DLB_BUS_WEIGHTS_DIFF_CS, 0x04030802},
42 	{DLB_BUS_WEIGHTS_DIFF_BG, 0x00000a02},
43 	{DLB_BUS_WEIGHTS_SAME_BG, 0x09000a01},
44 	{DLB_BUS_WEIGHTS_RD_WR, 0x00020005},
45 	{DLB_BUS_WEIGHTS_ATTR_SYS_PRIO, 0x00060f10},
46 	{DLB_MAIN_QUEUE_MAP, 0x00000543},
47 	{DLB_LINE_SPLIT, 0x00000000},
48 	{DLB_USER_COMMAND_REG, 0x00000000},
49 	{0x0, 0x0}
66 	{"a38x_customer_0_800", DDR_FREQ_800, 0, 0x0, A38X_CUSTOMER_BOARD_ID0,
68 	{"a38x_customer_1_800", DDR_FREQ_800, 0, 0x0, A38X_CUSTOMER_BOARD_ID1,
71 	{"a38x_533", DDR_FREQ_533, 0, 0x0, MARVELL_BOARD, ddr3_a38x_533},
72 	{"a38x_667", DDR_FREQ_667, 0, 0x0, MARVELL_BOARD, ddr3_a38x_667},
73 	{"a38x_800", DDR_FREQ_800, 0, 0x0, MARVELL_BOARD, ddr3_a38x_800},
74 	{"a38x_933", DDR_FREQ_933, 0, 0x0, MARVELL_BOARD, ddr3_a38x_933},
90  * set 0 (supported for A380 and AC3) to configure DUNIT in values set by
101 #define DEV_VERSION_ID_REG		0x1823c
103 #define REVISON_ID_MASK			0xf00
106 #define MV_88F68XX_Z1_ID		0x0
107 #define MV_88F68XX_A0_ID		0x4
109 #define MV_88F69XX_Z1_ID		0x2
150 	return &ddr3_dlb_config_table_a0[0];  in sys_env_dlb_config_ptr_get()
153 		return &ddr3_dlb_config_table_a0[0];  in sys_env_dlb_config_ptr_get()
155 		return &ddr3_dlb_config_table[0];  in sys_env_dlb_config_ptr_get()
188 	for (ui = 0; ui < num_of_win_regs; ui++)  in ddr3_restore_and_set_final_windows()
189 		reg_write((win_ctrl_reg + 0x4 * ui), win[ui]);  in ddr3_restore_and_set_final_windows()
199 	reg = 0x1fffffe1;  in ddr3_restore_and_set_final_windows()
200 	for (cs = 0; cs < MAX_CS; cs++) {  in ddr3_restore_and_set_final_windows()
220 	win_jump_index = 0x10;  in ddr3_save_and_set_training_windows()
229 	reg_write(ADDRESS_FILTERING_END_REGISTER, 0);  in ddr3_save_and_set_training_windows()
232 	cs_ena = tm->interface_params[0].as_bus_params[0].cs_bitmask;  in ddr3_save_and_set_training_windows()
235 	/* {0x000200e8}  -   Open Mbus Window - 2G */  in ddr3_save_and_set_training_windows()
236 	reg_write(REG_XBAR_WIN_19_CTRL_ADDR, 0);  in ddr3_save_and_set_training_windows()
239 	for (ui = 0; ui < num_of_win_regs; ui++)  in ddr3_save_and_set_training_windows()
240 		win[ui] = reg_read(win_ctrl_reg + 0x4 * ui);  in ddr3_save_and_set_training_windows()
243 	reg = 0;  in ddr3_save_and_set_training_windows()
244 	tmp_count = 0;  in ddr3_save_and_set_training_windows()
245 	for (cs = 0; cs < MAX_CS; cs++) {  in ddr3_save_and_set_training_windows()
248 			case 0:  in ddr3_save_and_set_training_windows()
249 				reg = 0x0e00;  in ddr3_save_and_set_training_windows()
252 				reg = 0x0d00;  in ddr3_save_and_set_training_windows()
255 				reg = 0x0b00;  in ddr3_save_and_set_training_windows()
258 				reg = 0x0700;  in ddr3_save_and_set_training_windows()
261 			reg |= (1 << 0);  in ddr3_save_and_set_training_windows()
262 			reg |= (SDRAM_CS_SIZE & 0xffff0000);  in ddr3_save_and_set_training_windows()
267 			       0xffff0000);  in ddr3_save_and_set_training_windows()
273 					  win_jump_index * tmp_count, 0);  in ddr3_save_and_set_training_windows()
291 	u32 reg = 0;  in ddr3_init()
307 	case 0x3:  in ddr3_init()
308 	case 0x1:  in ddr3_init()
310 	case 0x0:  in ddr3_init()
311 		reg_bit_set(CPU_CONFIGURATION_REG(0), CPU_MRVL_ID_OFFSET);  in ddr3_init()
328 	 * Stage 0 - Set board configuration  in ddr3_init()
342 	/* Fix read ready phases for all SOC in reg 0x15c8 */  in ddr3_init()
345 	reg |= 0x4;		/* Phase 0 */  in ddr3_init()
347 	reg |= (0x4 << (1 * REG_TRAINING_DEBUG_3_OFFS));	/* Phase 1 */  in ddr3_init()
349 	reg |= (0x6 << (3 * REG_TRAINING_DEBUG_3_OFFS));	/* Phase 3 */  in ddr3_init()
351 	reg |= (0x6 << (4 * REG_TRAINING_DEBUG_3_OFFS));  in ddr3_init()
353 	reg |= (0x6 << (5 * REG_TRAINING_DEBUG_3_OFFS));  in ddr3_init()
359 	 * Axi_data_bus_width[0] = 128bit  in ddr3_init()
361 	/* 0x14a8 - AXI Control Register */  in ddr3_init()
362 	reg_write(REG_DRAM_AXI_CTRL_ADDR, 0);  in ddr3_init()
375 	if (generic_init_controller == 0) {  in ddr3_init()
376 		ddr3_tip_init_specific_reg_config(0,  in ddr3_init()
384 	status = ddr3_hws_tune_training_params(0);  in ddr3_init()
443 	return 0;		/* No fabric */  in ddr3_get_fab_opt()
498 	for (i = 0; i < size; i++) {  in ddr3_get_static_ddr_mode()
507 	return 0;  in ddr3_get_static_ddr_mode()
520 	u32 cs_count = 0;  in ddr3_get_cs_num_from_reg()
523 	for (cs = 0; cs < MAX_CS; cs++) {  in ddr3_get_cs_num_from_reg()
540 	case 0x8:  in get_target_freq()
544 	case 0xc:  in get_target_freq()
549 		*ddr_freq = 0;  in get_target_freq()
550 		*hclk_ps = 0;  in get_target_freq()
562 	u32 reg, i = 0;  in ddr3_new_tip_dlb_config()
566 	while (config_table_ptr[i].reg_addr != 0) {  in ddr3_new_tip_dlb_config()
582 	u32 mem_total_size = 0;  in ddr3_fast_path_dynamic_cs_size_config()
583 	u32 cs_mem_size = 0;  in ddr3_fast_path_dynamic_cs_size_config()
593 	for (cs = 0; cs < MAX_CS; cs++) {  in ddr3_fast_path_dynamic_cs_size_config()
606 				[tm->interface_params[0].memory_size];  in ddr3_fast_path_dynamic_cs_size_config()
620 				printf("Updated Physical Mem size is from 0x%x to %x\n",  in ddr3_fast_path_dynamic_cs_size_config()
627 			reg = 0xffffe1;  in ddr3_fast_path_dynamic_cs_size_config()
629 			reg |= (cs_mem_size - 1) & 0xffff0000;  in ddr3_fast_path_dynamic_cs_size_config()
634 			reg = ((cs_mem_size) * cs) & 0xffff0000;  in ddr3_fast_path_dynamic_cs_size_config()
642 			 * cs_mem_size by 0x10000 (it is equal to >> 16)  in ddr3_fast_path_dynamic_cs_size_config()
647 			if (mem_total_size_c + cs_mem_size_c < 0x10000)  in ddr3_fast_path_dynamic_cs_size_config()
664 	bus_width = (reg_read(REG_SDRAM_CONFIG_ADDR) & 0x8000) >>  in ddr3_get_bus_width()
667 	return (bus_width == 0) ? 16 : 32;  in ddr3_get_bus_width()
675 			(0x3 << (REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS * cs))) >>  in ddr3_get_device_width()
678 	return (device_width == 0) ? 8 : 16;  in ddr3_get_device_width()
691 	device_size_low = (data >> cs_low_offset) & 0x3;  in ddr3_get_device_size()
692 	device_size_high = (data >> cs_high_offset) & 0x1;  in ddr3_get_device_size()
697 	case 0:  in ddr3_get_device_size()
714 		return 0;  in ddr3_get_device_size()
729 	 * so bit 15 in 0x1400, that means if whole bus used or only half,  in ddr3_calc_mem_cs_size()