Lines Matching refs:ba_intlv_ctl
877 popts->ba_intlv_ctl = 0; in populate_memctl_options()
1195 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1; in populate_memctl_options()
1198 popts->ba_intlv_ctl = FSL_DDR_CS2_CS3; in populate_memctl_options()
1201 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3; in populate_memctl_options()
1204 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3; in populate_memctl_options()
1207 popts->ba_intlv_ctl = auto_bank_intlv(pdimm); in populate_memctl_options()
1210 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { in populate_memctl_options()
1214 popts->ba_intlv_ctl = 0; in populate_memctl_options()
1225 popts->ba_intlv_ctl = 0; in populate_memctl_options()
1231 popts->ba_intlv_ctl = 0; in populate_memctl_options()
1240 popts->ba_intlv_ctl = 0; in populate_memctl_options()
1249 popts->ba_intlv_ctl = 0; in populate_memctl_options()
1255 popts->ba_intlv_ctl = 0; in populate_memctl_options()
1264 popts->ba_intlv_ctl = 0; in populate_memctl_options()
1271 popts->ba_intlv_ctl = 0; in populate_memctl_options()
1279 popts->ba_intlv_ctl = 0; in populate_memctl_options()