Lines Matching refs:ddr
29 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
45 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
49 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
54 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in fsl_ddr_set_memctl_regs()
59 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_set_memctl_regs()
71 out_be32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
94 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
95 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
96 out_be32(&ddr->cs0_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
99 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
100 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
101 out_be32(&ddr->cs1_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
104 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
105 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
106 out_be32(&ddr->cs2_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
109 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
110 out_be32(&ddr->cs3_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
111 out_be32(&ddr->cs3_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
115 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); in fsl_ddr_set_memctl_regs()
116 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); in fsl_ddr_set_memctl_regs()
117 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); in fsl_ddr_set_memctl_regs()
118 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
119 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); in fsl_ddr_set_memctl_regs()
120 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); in fsl_ddr_set_memctl_regs()
121 out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); in fsl_ddr_set_memctl_regs()
122 out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); in fsl_ddr_set_memctl_regs()
123 out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); in fsl_ddr_set_memctl_regs()
124 out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); in fsl_ddr_set_memctl_regs()
125 out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); in fsl_ddr_set_memctl_regs()
126 out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); in fsl_ddr_set_memctl_regs()
127 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); in fsl_ddr_set_memctl_regs()
128 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); in fsl_ddr_set_memctl_regs()
129 out_be32(&ddr->sdram_data_init, regs->ddr_data_init); in fsl_ddr_set_memctl_regs()
130 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); in fsl_ddr_set_memctl_regs()
131 out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4); in fsl_ddr_set_memctl_regs()
132 out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); in fsl_ddr_set_memctl_regs()
133 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); in fsl_ddr_set_memctl_regs()
134 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); in fsl_ddr_set_memctl_regs()
142 out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); in fsl_ddr_set_memctl_regs()
144 out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); in fsl_ddr_set_memctl_regs()
147 out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); in fsl_ddr_set_memctl_regs()
148 out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); in fsl_ddr_set_memctl_regs()
149 out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); in fsl_ddr_set_memctl_regs()
150 out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1); in fsl_ddr_set_memctl_regs()
153 out_be32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
155 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); in fsl_ddr_set_memctl_regs()
156 out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); in fsl_ddr_set_memctl_regs()
159 out_be32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
164 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); in fsl_ddr_set_memctl_regs()
165 out_be32(&ddr->init_addr, regs->ddr_init_addr); in fsl_ddr_set_memctl_regs()
166 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); in fsl_ddr_set_memctl_regs()
167 out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); in fsl_ddr_set_memctl_regs()
169 out_be32(&ddr->err_disable, regs->err_disable); in fsl_ddr_set_memctl_regs()
170 out_be32(&ddr->err_int_en, regs->err_int_en); in fsl_ddr_set_memctl_regs()
174 out_be32(&ddr->debug[i], regs->debug[i]); in fsl_ddr_set_memctl_regs()
179 out_be32(&ddr->debug[12], 0x00000015); in fsl_ddr_set_memctl_regs()
180 out_be32(&ddr->debug[21], 0x24000000); in fsl_ddr_set_memctl_regs()
200 out_be32(&ddr->sdram_cfg, temp_sdram_cfg); in fsl_ddr_set_memctl_regs()
204 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff); in fsl_ddr_set_memctl_regs()
205 out_be32(&ddr->debug[2], 0x00000400); in fsl_ddr_set_memctl_regs()
206 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff); in fsl_ddr_set_memctl_regs()
207 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff); in fsl_ddr_set_memctl_regs()
208 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb); in fsl_ddr_set_memctl_regs()
209 out_be32(&ddr->mtcr, 0); in fsl_ddr_set_memctl_regs()
210 save1 = in_be32(&ddr->debug[12]); in fsl_ddr_set_memctl_regs()
211 save2 = in_be32(&ddr->debug[21]); in fsl_ddr_set_memctl_regs()
212 out_be32(&ddr->debug[12], 0x00000015); in fsl_ddr_set_memctl_regs()
213 out_be32(&ddr->debug[21], 0x24000000); in fsl_ddr_set_memctl_regs()
214 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff); in fsl_ddr_set_memctl_regs()
215 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN); in fsl_ddr_set_memctl_regs()
218 while (!(in_be32(&ddr->debug[1]) & 0x2)) in fsl_ddr_set_memctl_regs()
223 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
232 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
234 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
243 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
252 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
254 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
263 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
272 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
274 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
283 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
292 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
294 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
303 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
312 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
314 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
325 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000) in fsl_ddr_set_memctl_regs()
328 out_be32(&ddr->sdram_cfg, temp_sdram_cfg); in fsl_ddr_set_memctl_regs()
329 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
330 out_be32(&ddr->debug[2], 0x0); in fsl_ddr_set_memctl_regs()
331 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); in fsl_ddr_set_memctl_regs()
332 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); in fsl_ddr_set_memctl_regs()
333 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); in fsl_ddr_set_memctl_regs()
334 out_be32(&ddr->debug[12], save1); in fsl_ddr_set_memctl_regs()
335 out_be32(&ddr->debug[21], save2); in fsl_ddr_set_memctl_regs()
336 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); in fsl_ddr_set_memctl_regs()
347 if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2) in fsl_ddr_set_memctl_regs()
348 && in_be32(&ddr->sdram_cfg) & 0x80000) { in fsl_ddr_set_memctl_regs()
350 setbits_be32(&ddr->debug[0], 1); in fsl_ddr_set_memctl_regs()
365 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT); in fsl_ddr_set_memctl_regs()
367 in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
370 setbits_be32(&ddr->debug[2], 0x400); in fsl_ddr_set_memctl_regs()
371 debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); in fsl_ddr_set_memctl_regs()
387 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); in fsl_ddr_set_memctl_regs()
390 temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI); in fsl_ddr_set_memctl_regs()
393 temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI); in fsl_ddr_set_memctl_regs()
396 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); in fsl_ddr_set_memctl_regs()
421 bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) in fsl_ddr_set_memctl_regs()
433 while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && in fsl_ddr_set_memctl_regs()
446 clrbits_be32(&ddr->debug[2], 0x400); in fsl_ddr_set_memctl_regs()
447 debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); in fsl_ddr_set_memctl_regs()
451 clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK); in fsl_ddr_set_memctl_regs()
453 in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
456 setbits_be32(&ddr->debug[0], 0x10000); in fsl_ddr_set_memctl_regs()
457 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); in fsl_ddr_set_memctl_regs()
460 setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK); in fsl_ddr_set_memctl_regs()
462 in_be32(&ddr->timing_cfg_2)); in fsl_ddr_set_memctl_regs()
465 out_be32(&ddr->debug[5], 0x9f9f9f9f); in fsl_ddr_set_memctl_regs()
466 debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5])); in fsl_ddr_set_memctl_regs()
469 out_be32(&ddr->debug[6], 0x9f9f9f9f); in fsl_ddr_set_memctl_regs()
470 debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6])); in fsl_ddr_set_memctl_regs()
473 setbits_be32(&ddr->debug[1], 0x800); in fsl_ddr_set_memctl_regs()
474 debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1])); in fsl_ddr_set_memctl_regs()
477 while (in_be32(&ddr->debug[1]) & 0x800) in fsl_ddr_set_memctl_regs()
481 clrbits_be32(&ddr->debug[0], 0x10000); in fsl_ddr_set_memctl_regs()
482 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); in fsl_ddr_set_memctl_regs()
485 setbits_be32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
487 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
491 setbits_be32(&ddr->debug[1], 0x400); in fsl_ddr_set_memctl_regs()
492 debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1])); in fsl_ddr_set_memctl_regs()
495 while (in_be32(&ddr->debug[1]) & 0x400) in fsl_ddr_set_memctl_regs()
503 setbits_be32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
505 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
510 while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && in fsl_ddr_set_memctl_regs()
528 setbits_be32(&ddr->sdram_cfg, 0x2); /* MEM_HALT */ in fsl_ddr_set_memctl_regs()
531 out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds); in fsl_ddr_set_memctl_regs()
534 out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds); in fsl_ddr_set_memctl_regs()
538 out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds); in fsl_ddr_set_memctl_regs()
541 out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds); in fsl_ddr_set_memctl_regs()
545 clrbits_be32(&ddr->sdram_cfg, 0x2); in fsl_ddr_set_memctl_regs()
551 clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); in fsl_ddr_set_memctl_regs()