Lines Matching refs:pinfo
240 static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, in __step_assign_addresses() argument
246 unsigned int first_ctrl = pinfo->first_ctrl; in __step_assign_addresses()
247 unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1; in __step_assign_addresses()
258 switch (pinfo->memctl_opts[i].data_bus_width) { in __step_assign_addresses()
263 if (!pinfo->dimm_params[i][j].n_ranks) in __step_assign_addresses()
265 dw = pinfo->dimm_params[i][j].primary_sdram_width; in __step_assign_addresses()
280 dw = pinfo->dimm_params[i][j].data_width; in __step_assign_addresses()
281 if (pinfo->dimm_params[i][j].n_ranks in __step_assign_addresses()
309 current_mem_base = pinfo->mem_base; in __step_assign_addresses()
311 if (pinfo->memctl_opts[first_ctrl].memctl_interleaving) { in __step_assign_addresses()
312 rank_density = pinfo->dimm_params[first_ctrl][0].rank_density >> in __step_assign_addresses()
314 switch (pinfo->memctl_opts[first_ctrl].ba_intlv_ctl & in __step_assign_addresses()
331 if (pinfo->memctl_opts[i].memctl_interleaving) { in __step_assign_addresses()
332 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { in __step_assign_addresses()
353 pinfo->common_timing_params[i].base_address = in __step_assign_addresses()
355 pinfo->common_timing_params[i].total_mem = in __step_assign_addresses()
364 pinfo->common_timing_params[i].base_address = in __step_assign_addresses()
368 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; in __step_assign_addresses()
369 pinfo->dimm_params[i][j].base_address = in __step_assign_addresses()
376 pinfo->common_timing_params[i].total_mem = in __step_assign_addresses()
388 pinfo->common_timing_params[i].base_address = in __step_assign_addresses()
393 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; in __step_assign_addresses()
394 pinfo->dimm_params[i][j].base_address = in __step_assign_addresses()
401 pinfo->common_timing_params[i].total_mem = in __step_assign_addresses()
413 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
417 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, in fsl_ddr_compute() argument
423 unsigned int first_ctrl = pinfo->first_ctrl; in fsl_ddr_compute()
424 unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1; in fsl_ddr_compute()
427 __maybe_unused int dimm_slots_per_ctrl = pinfo->dimm_slots_per_ctrl; in fsl_ddr_compute()
429 fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg; in fsl_ddr_compute()
430 common_timing_params_t *timing_params = pinfo->common_timing_params; in fsl_ddr_compute()
431 if (pinfo->board_need_mem_reset) in fsl_ddr_compute()
432 assert_reset = pinfo->board_need_mem_reset(); in fsl_ddr_compute()
448 fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i, in fsl_ddr_compute()
458 &(pinfo->spd_installed_dimms[i][j]); in fsl_ddr_compute()
460 &(pinfo->dimm_params[i][j]); in fsl_ddr_compute()
505 &(pinfo->dimm_params[i][j]); in fsl_ddr_compute()
521 pinfo->dimm_params[i], in fsl_ddr_compute()
539 &pinfo->memctl_opts[i], in fsl_ddr_compute()
540 pinfo->dimm_params[i], i); in fsl_ddr_compute()
551 if (pinfo->board_mem_reset) { in fsl_ddr_compute()
553 pinfo->board_mem_reset(); in fsl_ddr_compute()
561 check_interleaving_options(pinfo); in fsl_ddr_compute()
562 total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust); in fsl_ddr_compute()
577 &pinfo->memctl_opts[i], in fsl_ddr_compute()
579 pinfo->dimm_params[i], in fsl_ddr_compute()
617 0xFFFFFFULL) - pinfo->mem_base; in fsl_ddr_compute()
623 phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo) in __fsl_ddr_sdram() argument
632 first_ctrl = pinfo->first_ctrl; in __fsl_ddr_sdram()
633 last_ctrl = first_ctrl + pinfo->num_ctrls - 1; in __fsl_ddr_sdram()
638 total_memory = fsl_ddr_interactive(pinfo, 0); in __fsl_ddr_sdram()
640 total_memory = fsl_ddr_interactive(pinfo, 1); in __fsl_ddr_sdram()
643 total_memory = fsl_ddr_compute(pinfo, STEP_GET_SPD, 0); in __fsl_ddr_sdram()
646 switch (pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode) { in __fsl_ddr_sdram()
651 pinfo->memctl_opts[first_ctrl]. in __fsl_ddr_sdram()
668 if (pinfo->board_need_mem_reset) in __fsl_ddr_sdram()
669 deassert_reset = pinfo->board_need_mem_reset(); in __fsl_ddr_sdram()
671 if (pinfo->common_timing_params[i].all_dimms_registered) in __fsl_ddr_sdram()
676 if (pinfo->common_timing_params[i].ndimms_present == 0) { in __fsl_ddr_sdram()
685 fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i, in __fsl_ddr_sdram()
690 if (pinfo->board_mem_de_reset) { in __fsl_ddr_sdram()
692 pinfo->board_mem_de_reset(); in __fsl_ddr_sdram()
698 fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), in __fsl_ddr_sdram()
710 if (pinfo->memctl_opts[i].memctl_interleaving) { in __fsl_ddr_sdram()
711 switch (pinfo->memctl_opts[i]. in __fsl_ddr_sdram()
722 &pinfo->common_timing_params[i], in __fsl_ddr_sdram()
729 &pinfo->common_timing_params[i], in __fsl_ddr_sdram()
740 &pinfo->common_timing_params[i], in __fsl_ddr_sdram()
750 &pinfo->common_timing_params[i], in __fsl_ddr_sdram()
774 fsl_ddr_set_lawbar(&pinfo->common_timing_params[i], in __fsl_ddr_sdram()