Lines Matching refs:i
148 unsigned int i; in fsl_ddr_get_spd() local
156 for (i = 0; i < dimm_slots_per_ctrl; i++) { in fsl_ddr_get_spd()
157 i2c_address = spd_i2c_addr[ctrl_num][i]; in fsl_ddr_get_spd()
158 update_spd_address(ctrl_num, i, &i2c_address); in fsl_ddr_get_spd()
159 get_spd(&(ctrl_dimms_spd[i]), i2c_address); in fsl_ddr_get_spd()
243 unsigned int i, j; in __step_assign_addresses() local
255 for (i = first_ctrl; i <= last_ctrl; i++) { in __step_assign_addresses()
258 switch (pinfo->memctl_opts[i].data_bus_width) { in __step_assign_addresses()
263 if (!pinfo->dimm_params[i][j].n_ranks) in __step_assign_addresses()
265 dw = pinfo->dimm_params[i][j].primary_sdram_width; in __step_assign_addresses()
267 dbw_cap_adj[i] = 2; in __step_assign_addresses()
270 dbw_cap_adj[i] = 1; in __step_assign_addresses()
280 dw = pinfo->dimm_params[i][j].data_width; in __step_assign_addresses()
281 if (pinfo->dimm_params[i][j].n_ranks in __step_assign_addresses()
293 dbw_cap_adj[i] = 1; in __step_assign_addresses()
303 "specified controller %u\n", i); in __step_assign_addresses()
306 debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]); in __step_assign_addresses()
330 for (i = first_ctrl; i <= last_ctrl; i++) { in __step_assign_addresses()
331 if (pinfo->memctl_opts[i].memctl_interleaving) { in __step_assign_addresses()
332 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { in __step_assign_addresses()
353 pinfo->common_timing_params[i].base_address = in __step_assign_addresses()
355 pinfo->common_timing_params[i].total_mem = in __step_assign_addresses()
358 debug("ctrl %d base 0x%llx\n", i, current_mem_base); in __step_assign_addresses()
359 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); in __step_assign_addresses()
364 pinfo->common_timing_params[i].base_address = in __step_assign_addresses()
368 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; in __step_assign_addresses()
369 pinfo->dimm_params[i][j].base_address = in __step_assign_addresses()
371 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); in __step_assign_addresses()
375 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); in __step_assign_addresses()
376 pinfo->common_timing_params[i].total_mem = in __step_assign_addresses()
386 for (i = first_ctrl; i <= last_ctrl; i++) { in __step_assign_addresses()
388 pinfo->common_timing_params[i].base_address = in __step_assign_addresses()
393 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; in __step_assign_addresses()
394 pinfo->dimm_params[i][j].base_address = in __step_assign_addresses()
396 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); in __step_assign_addresses()
400 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); in __step_assign_addresses()
401 pinfo->common_timing_params[i].total_mem = in __step_assign_addresses()
420 unsigned int i, j; in fsl_ddr_compute() local
437 for (i = first_ctrl; i <= last_ctrl; i++) in fsl_ddr_compute()
438 dbw_capacity_adjust[i] = 0; in fsl_ddr_compute()
447 for (i = first_ctrl; i <= last_ctrl; i++) { in fsl_ddr_compute()
448 fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i, in fsl_ddr_compute()
455 for (i = first_ctrl; i <= last_ctrl; i++) { in fsl_ddr_compute()
458 &(pinfo->spd_installed_dimms[i][j]); in fsl_ddr_compute()
460 &(pinfo->dimm_params[i][j]); in fsl_ddr_compute()
462 i, spd, pdimm, j); in fsl_ddr_compute()
467 "calculation\n", i); in fsl_ddr_compute()
469 i, j); in fsl_ddr_compute()
475 "for memctl=%u dimm=%u\n", i, j); in fsl_ddr_compute()
482 "dimm=%u\n", i, j); in fsl_ddr_compute()
502 for (i = first_ctrl; i <= last_ctrl; i++) { in fsl_ddr_compute()
505 &(pinfo->dimm_params[i][j]); in fsl_ddr_compute()
506 fsl_ddr_get_dimm_params(pdimm, i, j); in fsl_ddr_compute()
516 for (i = first_ctrl; i <= last_ctrl; i++) { in fsl_ddr_compute()
518 " parameters for memctl=%u\n", i); in fsl_ddr_compute()
520 (i, in fsl_ddr_compute()
521 pinfo->dimm_params[i], in fsl_ddr_compute()
522 &timing_params[i], in fsl_ddr_compute()
528 for (i = first_ctrl; i <= last_ctrl; i++) { in fsl_ddr_compute()
530 "configuration options for memctl=%u\n", i); in fsl_ddr_compute()
538 &timing_params[i], in fsl_ddr_compute()
539 &pinfo->memctl_opts[i], in fsl_ddr_compute()
540 pinfo->dimm_params[i], i); in fsl_ddr_compute()
547 if (timing_params[i].all_dimms_registered) in fsl_ddr_compute()
568 for (i = first_ctrl; i <= last_ctrl; i++) { in fsl_ddr_compute()
569 if (timing_params[i].ndimms_present == 0) { in fsl_ddr_compute()
570 memset(&ddr_reg[i], 0, in fsl_ddr_compute()
576 (i, in fsl_ddr_compute()
577 &pinfo->memctl_opts[i], in fsl_ddr_compute()
578 &ddr_reg[i], &timing_params[i], in fsl_ddr_compute()
579 pinfo->dimm_params[i], in fsl_ddr_compute()
580 dbw_capacity_adjust[i], in fsl_ddr_compute()
597 for (i = first_ctrl; i <= last_ctrl; i++) { in fsl_ddr_compute()
599 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i]; in fsl_ddr_compute()
625 unsigned int i, first_ctrl, last_ctrl; in __fsl_ddr_sdram() local
670 for (i = first_ctrl; i <= last_ctrl; i++) { in __fsl_ddr_sdram()
671 if (pinfo->common_timing_params[i].all_dimms_registered) in __fsl_ddr_sdram()
674 for (i = first_ctrl; i <= last_ctrl; i++) { in __fsl_ddr_sdram()
675 debug("Programming controller %u\n", i); in __fsl_ddr_sdram()
676 if (pinfo->common_timing_params[i].ndimms_present == 0) { in __fsl_ddr_sdram()
678 "skipping programming\n", i); in __fsl_ddr_sdram()
685 fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i, in __fsl_ddr_sdram()
696 for (i = first_ctrl; i <= last_ctrl; i++) { in __fsl_ddr_sdram()
698 fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), in __fsl_ddr_sdram()
699 i, 2); in __fsl_ddr_sdram()
709 for (i = first_ctrl; i <= last_ctrl; i++) { in __fsl_ddr_sdram()
710 if (pinfo->memctl_opts[i].memctl_interleaving) { in __fsl_ddr_sdram()
711 switch (pinfo->memctl_opts[i]. in __fsl_ddr_sdram()
717 if (i % 2) in __fsl_ddr_sdram()
719 if (i == 0) { in __fsl_ddr_sdram()
722 &pinfo->common_timing_params[i], in __fsl_ddr_sdram()
723 law_memctl, i); in __fsl_ddr_sdram()
726 else if (i == 2) { in __fsl_ddr_sdram()
729 &pinfo->common_timing_params[i], in __fsl_ddr_sdram()
730 law_memctl, i); in __fsl_ddr_sdram()
738 if (i == 0) { in __fsl_ddr_sdram()
740 &pinfo->common_timing_params[i], in __fsl_ddr_sdram()
741 law_memctl, i); in __fsl_ddr_sdram()
748 if (i == 0) in __fsl_ddr_sdram()
750 &pinfo->common_timing_params[i], in __fsl_ddr_sdram()
751 law_memctl, i); in __fsl_ddr_sdram()
758 switch (i) { in __fsl_ddr_sdram()
774 fsl_ddr_set_lawbar(&pinfo->common_timing_params[i], in __fsl_ddr_sdram()
775 law_memctl, i); in __fsl_ddr_sdram()