2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
4  * SPDX-License-Identifier:	GPL-2.0
8  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
24  * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
51 	[0][0] = SPD_EEPROM_ADDRESS1,	/* controller 1 */
52 	[0][1] = SPD_EEPROM_ADDRESS2,	/* controller 1 */
56 	[0][0] = SPD_EEPROM_ADDRESS1,	/* controller 1 */
57 	[1][0] = SPD_EEPROM_ADDRESS2,	/* controller 2 */
61 	[0][0] = SPD_EEPROM_ADDRESS1,	/* controller 1 */
62 	[0][1] = SPD_EEPROM_ADDRESS2,	/* controller 1 */
63 	[1][0] = SPD_EEPROM_ADDRESS3,	/* controller 2 */
64 	[1][1] = SPD_EEPROM_ADDRESS4,	/* controller 2 */
68 	[0][0] = SPD_EEPROM_ADDRESS1,	/* controller 1 */
69 	[1][0] = SPD_EEPROM_ADDRESS2,	/* controller 2 */
70 	[2][0] = SPD_EEPROM_ADDRESS3,	/* controller 3 */
74 	[0][0] = SPD_EEPROM_ADDRESS1,	/* controller 1 */
75 	[0][1] = SPD_EEPROM_ADDRESS2,	/* controller 1 */
76 	[1][0] = SPD_EEPROM_ADDRESS3,	/* controller 2 */
77 	[1][1] = SPD_EEPROM_ADDRESS4,	/* controller 2 */
78 	[2][0] = SPD_EEPROM_ADDRESS5,	/* controller 3 */
79 	[2][1] = SPD_EEPROM_ADDRESS6,	/* controller 3 */
101 	 * See Jedec standar No. 21-C for detail  in __get_spd()
110 				   (int)sizeof(generic_spd_eeprom_t) - 256));  in __get_spd()
171  *    - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
172  *    - Same memory data bus width on all controllers
176  * The memory controller and associated documentation use confusing
181  * memory controller/documention  |industry   |this code  |signals
182  * -------------------------------|-----------|-----------|-----------------
184  * logical bank/sub-bank	  |bank       |bank	  |bank address (BA)
189  * memory controller interleaving feature, where accesses are interleaved
190  * _BETWEEN_ two seperate memory controllers.  This is configured only in
191  * CS0_CONFIG[INTLV_CTL] of each memory controller.
193  * memory controller documentation | number of chip selects
194  *				   | per memory controller supported
195  * --------------------------------|-----------------------------------------
201  *				   |   mode used on every memory controller
204  * _WITHIN_ each memory controller.  The feature is referred to in
209  * -----------------------------|-----------------------|------------------
246 	unsigned int first_ctrl = pinfo->first_ctrl;  in __step_assign_addresses()
247 	unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;  in __step_assign_addresses()
258 		switch (pinfo->memctl_opts[i].data_bus_width) {  in __step_assign_addresses()
260 			/* 16-bit */  in __step_assign_addresses()
263 				if (!pinfo->dimm_params[i][j].n_ranks)  in __step_assign_addresses()
265 				dw = pinfo->dimm_params[i][j].primary_sdram_width;  in __step_assign_addresses()
277 			/* 32-bit */  in __step_assign_addresses()
280 				dw = pinfo->dimm_params[i][j].data_width;  in __step_assign_addresses()
281 				if (pinfo->dimm_params[i][j].n_ranks  in __step_assign_addresses()
286 					 * further reduces the memory  in __step_assign_addresses()
298 			/* 64-bit */  in __step_assign_addresses()
303 				"specified controller %u\n", i);  in __step_assign_addresses()
309 	current_mem_base = pinfo->mem_base;  in __step_assign_addresses()
311 	if (pinfo->memctl_opts[first_ctrl].memctl_interleaving) {  in __step_assign_addresses()
312 		rank_density = pinfo->dimm_params[first_ctrl][0].rank_density >>  in __step_assign_addresses()
314 		switch (pinfo->memctl_opts[first_ctrl].ba_intlv_ctl &  in __step_assign_addresses()
331 			if (pinfo->memctl_opts[i].memctl_interleaving) {  in __step_assign_addresses()
332 				switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {  in __step_assign_addresses()
353 				pinfo->common_timing_params[i].base_address =  in __step_assign_addresses()
355 				pinfo->common_timing_params[i].total_mem =  in __step_assign_addresses()
361 				/* when 3rd controller not interleaved */  in __step_assign_addresses()
364 				pinfo->common_timing_params[i].base_address =  in __step_assign_addresses()
368 						pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];  in __step_assign_addresses()
369 					pinfo->dimm_params[i][j].base_address =  in __step_assign_addresses()
376 				pinfo->common_timing_params[i].total_mem =  in __step_assign_addresses()
383 		 * Simple linear assignment if memory  in __step_assign_addresses()
388 			pinfo->common_timing_params[i].base_address =  in __step_assign_addresses()
393 					pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];  in __step_assign_addresses()
394 				pinfo->dimm_params[i][j].base_address =  in __step_assign_addresses()
401 			pinfo->common_timing_params[i].total_mem =  in __step_assign_addresses()
423 	unsigned int first_ctrl =  pinfo->first_ctrl;  in fsl_ddr_compute()
424 	unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;  in fsl_ddr_compute()
427 	__maybe_unused int dimm_slots_per_ctrl = pinfo->dimm_slots_per_ctrl;  in fsl_ddr_compute()
429 	fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;  in fsl_ddr_compute()
430 	common_timing_params_t *timing_params = pinfo->common_timing_params;  in fsl_ddr_compute()
431 	if (pinfo->board_need_mem_reset)  in fsl_ddr_compute()
432 		assert_reset = pinfo->board_need_mem_reset();  in fsl_ddr_compute()
448 			fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i,  in fsl_ddr_compute()
458 					&(pinfo->spd_installed_dimms[i][j]);  in fsl_ddr_compute()
460 					&(pinfo->dimm_params[i][j]);  in fsl_ddr_compute()
465 					printf("SPD error on controller %d! "  in fsl_ddr_compute()
474 					" non-zero returned FATAL value "  in fsl_ddr_compute()
481 					" non-zero return value for memctl=%u "  in fsl_ddr_compute()
491 			 * Throw an error if this is for main memory, i.e.  in fsl_ddr_compute()
493 			 * as the memory size.  in fsl_ddr_compute()
505 					&(pinfo->dimm_params[i][j]);  in fsl_ddr_compute()
514 		 * suitable for all of the DIMMs on each memory controller  in fsl_ddr_compute()
521 				 pinfo->dimm_params[i],  in fsl_ddr_compute()
529 			debug("Reloading memory controller "  in fsl_ddr_compute()
532 			 * This "reloads" the memory controller options  in fsl_ddr_compute()
539 					&pinfo->memctl_opts[i],  in fsl_ddr_compute()
540 					pinfo->dimm_params[i], i);  in fsl_ddr_compute()
551 			if (pinfo->board_mem_reset) {  in fsl_ddr_compute()
553 				pinfo->board_mem_reset();  in fsl_ddr_compute()
566 		/* STEP 6:  compute controller register values */  in fsl_ddr_compute()
567 		debug("FSL Memory ctrl register computation\n");  in fsl_ddr_compute()
577 				 &pinfo->memctl_opts[i],  in fsl_ddr_compute()
579 				 pinfo->dimm_params[i],  in fsl_ddr_compute()
590 		 * Compute the amount of memory available just by  in fsl_ddr_compute()
593 		 * only CS0 when using dual-rank DIMMs.  in fsl_ddr_compute()
600 				if (reg->cs[j].config & 0x80000000) {  in fsl_ddr_compute()
606 					if (reg->cs[j].bnds == 0xffffffff)  in fsl_ddr_compute()
608 					end = reg->cs[j].bnds & 0xffff;  in fsl_ddr_compute()
617 			    0xFFFFFFULL) - pinfo->mem_base;  in fsl_ddr_compute()
632 	first_ctrl = pinfo->first_ctrl;  in __fsl_ddr_sdram()
633 	last_ctrl = first_ctrl + pinfo->num_ctrls - 1;  in __fsl_ddr_sdram()
645 	/* setup 3-way interleaving before enabling DDRC */  in __fsl_ddr_sdram()
646 	switch (pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode) {  in __fsl_ddr_sdram()
651 			pinfo->memctl_opts[first_ctrl].  in __fsl_ddr_sdram()
665 	 * For non-registered DIMMs, initialization can go through but it is  in __fsl_ddr_sdram()
668 	if (pinfo->board_need_mem_reset)  in __fsl_ddr_sdram()
669 		deassert_reset = pinfo->board_need_mem_reset();  in __fsl_ddr_sdram()
671 		if (pinfo->common_timing_params[i].all_dimms_registered)  in __fsl_ddr_sdram()
675 		debug("Programming controller %u\n", i);  in __fsl_ddr_sdram()
676 		if (pinfo->common_timing_params[i].ndimms_present == 0) {  in __fsl_ddr_sdram()
677 			debug("No dimms present on controller %u; "  in __fsl_ddr_sdram()
683 		 * the controller. It has to finish with step = 2 later.  in __fsl_ddr_sdram()
685 		fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i,  in __fsl_ddr_sdram()
690 		if (pinfo->board_mem_de_reset) {  in __fsl_ddr_sdram()
692 			pinfo->board_mem_de_reset();  in __fsl_ddr_sdram()
698 			fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]),  in __fsl_ddr_sdram()
710 		if (pinfo->memctl_opts[i].memctl_interleaving) {  in __fsl_ddr_sdram()
711 			switch (pinfo->memctl_opts[i].  in __fsl_ddr_sdram()
722 						&pinfo->common_timing_params[i],  in __fsl_ddr_sdram()
729 						&pinfo->common_timing_params[i],  in __fsl_ddr_sdram()
740 						&pinfo->common_timing_params[i],  in __fsl_ddr_sdram()
750 						&pinfo->common_timing_params[i],  in __fsl_ddr_sdram()
752 				/* place holder for future 4-way interleaving */  in __fsl_ddr_sdram()
774 			fsl_ddr_set_lawbar(&pinfo->common_timing_params[i],  in __fsl_ddr_sdram()
786 		print_size(total_memory, " of memory\n");  in __fsl_ddr_sdram()
787 		printf("       This U-Boot only supports < 4G of DDR\n");  in __fsl_ddr_sdram()
789 		printf("       "); /* re-align to match init_dram print */  in __fsl_ddr_sdram()
798  * fsl_ddr_sdram(void) -- this is the main function to be
801  * It returns amount of memory configured in bytes.
847  * fsl_ddr_sdram_size(first_ctrl, last_intlv) - This function only returns the
848  * size of the total memory without setting ddr control registers.