Lines Matching refs:ddr
148 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, in set_csn_config() argument
225 ddr->cs[i].config = (0 in set_csn_config()
244 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config); in set_csn_config()
249 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) in set_csn_config_2() argument
253 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24); in set_csn_config_2()
254 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); in set_csn_config_2()
295 fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_0() argument
438 ddr->timing_cfg_0 = (0 in set_timing_cfg_0()
448 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); in set_timing_cfg_0()
454 fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_3() argument
491 ddr->timing_cfg_3 = (0 in set_timing_cfg_3()
501 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); in set_timing_cfg_3()
506 fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_1() argument
619 ddr->timing_cfg_1 = (0 in set_timing_cfg_1()
629 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); in set_timing_cfg_1()
634 fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_2() argument
712 ddr->timing_cfg_2 = (0 in set_timing_cfg_2()
722 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); in set_timing_cfg_2()
726 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_rcw() argument
733 ddr->ddr_sdram_rcw_1 = popts->rcw_1; in set_ddr_sdram_rcw()
734 ddr->ddr_sdram_rcw_2 = popts->rcw_2; in set_ddr_sdram_rcw()
736 ddr->ddr_sdram_rcw_1 = in set_ddr_sdram_rcw()
745 ddr->ddr_sdram_rcw_2 = in set_ddr_sdram_rcw()
755 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1); in set_ddr_sdram_rcw()
756 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2); in set_ddr_sdram_rcw()
761 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_cfg() argument
827 ddr->ddr_sdram_cfg = (0 in set_ddr_sdram_cfg()
847 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg); in set_ddr_sdram_cfg()
852 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_cfg_2() argument
918 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE; in set_ddr_sdram_cfg_2()
919 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init); in set_ddr_sdram_cfg_2()
929 ddr->ddr_sdram_cfg_2 = (0 in set_ddr_sdram_cfg_2()
948 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); in set_ddr_sdram_cfg_2()
954 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_mode_2() argument
995 ddr->ddr_sdram_mode_2 = (0 in set_ddr_sdram_mode_2()
999 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); in set_ddr_sdram_mode_2()
1012 ddr->ddr_sdram_mode_4 = (0 in set_ddr_sdram_mode_2()
1018 ddr->ddr_sdram_mode_6 = (0 in set_ddr_sdram_mode_2()
1024 ddr->ddr_sdram_mode_8 = (0 in set_ddr_sdram_mode_2()
1032 ddr->ddr_sdram_mode_4); in set_ddr_sdram_mode_2()
1034 ddr->ddr_sdram_mode_6); in set_ddr_sdram_mode_2()
1036 ddr->ddr_sdram_mode_8); in set_ddr_sdram_mode_2()
1042 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_mode_2() argument
1070 ddr->ddr_sdram_mode_2 = (0 in set_ddr_sdram_mode_2()
1074 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); in set_ddr_sdram_mode_2()
1087 ddr->ddr_sdram_mode_4 = (0 in set_ddr_sdram_mode_2()
1093 ddr->ddr_sdram_mode_6 = (0 in set_ddr_sdram_mode_2()
1099 ddr->ddr_sdram_mode_8 = (0 in set_ddr_sdram_mode_2()
1107 ddr->ddr_sdram_mode_4); in set_ddr_sdram_mode_2()
1109 ddr->ddr_sdram_mode_6); in set_ddr_sdram_mode_2()
1111 ddr->ddr_sdram_mode_8); in set_ddr_sdram_mode_2()
1118 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_mode_2() argument
1126 ddr->ddr_sdram_mode_2 = (0 in set_ddr_sdram_mode_2()
1130 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); in set_ddr_sdram_mode_2()
1136 static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_mode_9() argument
1149 if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) && in set_ddr_sdram_mode_9()
1150 (ddr->cs[1].config & SDRAM_CS_CONFIG_EN) && in set_ddr_sdram_mode_9()
1151 (ddr->cs[2].config & SDRAM_CS_CONFIG_EN) && in set_ddr_sdram_mode_9()
1152 (ddr->cs[3].config & SDRAM_CS_CONFIG_EN)) in set_ddr_sdram_mode_9()
1155 if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) { in set_ddr_sdram_mode_9()
1163 if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { in set_ddr_sdram_mode_9()
1175 ddr->ddr_sdram_mode_9 = (0 in set_ddr_sdram_mode_9()
1185 debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9); in set_ddr_sdram_mode_9()
1189 (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) { in set_ddr_sdram_mode_9()
1196 if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { in set_ddr_sdram_mode_9()
1211 ddr->ddr_sdram_mode_11 = (0 in set_ddr_sdram_mode_9()
1217 ddr->ddr_sdram_mode_13 = (0 in set_ddr_sdram_mode_9()
1223 ddr->ddr_sdram_mode_15 = (0 in set_ddr_sdram_mode_9()
1231 ddr->ddr_sdram_mode_11); in set_ddr_sdram_mode_9()
1233 ddr->ddr_sdram_mode_13); in set_ddr_sdram_mode_9()
1235 ddr->ddr_sdram_mode_15); in set_ddr_sdram_mode_9()
1241 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_mode_10() argument
1256 ddr->ddr_sdram_mode_10 = (0 in set_ddr_sdram_mode_10()
1260 debug("FSLDDR: ddr_sdram_mode_10) = 0x%08x\n", ddr->ddr_sdram_mode_10); in set_ddr_sdram_mode_10()
1265 ddr->ddr_sdram_mode_12 = (0 in set_ddr_sdram_mode_10()
1271 ddr->ddr_sdram_mode_14 = (0 in set_ddr_sdram_mode_10()
1277 ddr->ddr_sdram_mode_16 = (0 in set_ddr_sdram_mode_10()
1285 ddr->ddr_sdram_mode_12); in set_ddr_sdram_mode_10()
1287 ddr->ddr_sdram_mode_14); in set_ddr_sdram_mode_10()
1289 ddr->ddr_sdram_mode_16); in set_ddr_sdram_mode_10()
1297 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_interval() argument
1309 ddr->ddr_sdram_interval = (0 in set_ddr_sdram_interval()
1313 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval); in set_ddr_sdram_interval()
1319 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_mode() argument
1441 ddr->ddr_sdram_mode = (0 in set_ddr_sdram_mode()
1446 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); in set_ddr_sdram_mode()
1459 ddr->ddr_sdram_mode_3 = (0 in set_ddr_sdram_mode()
1465 ddr->ddr_sdram_mode_5 = (0 in set_ddr_sdram_mode()
1471 ddr->ddr_sdram_mode_7 = (0 in set_ddr_sdram_mode()
1479 ddr->ddr_sdram_mode_3); in set_ddr_sdram_mode()
1481 ddr->ddr_sdram_mode_5); in set_ddr_sdram_mode()
1483 ddr->ddr_sdram_mode_5); in set_ddr_sdram_mode()
1490 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_mode() argument
1632 ddr->ddr_sdram_mode = (0 in set_ddr_sdram_mode()
1637 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); in set_ddr_sdram_mode()
1654 ddr->ddr_sdram_mode_3 = (0 in set_ddr_sdram_mode()
1660 ddr->ddr_sdram_mode_5 = (0 in set_ddr_sdram_mode()
1666 ddr->ddr_sdram_mode_7 = (0 in set_ddr_sdram_mode()
1674 ddr->ddr_sdram_mode_3); in set_ddr_sdram_mode()
1676 ddr->ddr_sdram_mode_5); in set_ddr_sdram_mode()
1678 ddr->ddr_sdram_mode_5); in set_ddr_sdram_mode()
1686 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_mode() argument
1806 ddr->ddr_sdram_mode = (0 in set_ddr_sdram_mode()
1810 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); in set_ddr_sdram_mode()
1815 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr) in set_ddr_data_init() argument
1824 ddr->ddr_data_init = init_value; in set_ddr_data_init()
1832 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_clk_cntl() argument
1850 ddr->ddr_sdram_clk_cntl = (0 in set_ddr_sdram_clk_cntl()
1854 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl); in set_ddr_sdram_clk_cntl()
1858 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr) in set_ddr_init_addr() argument
1862 ddr->ddr_init_addr = init_addr; in set_ddr_init_addr()
1866 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr) in set_ddr_init_ext_addr() argument
1871 ddr->ddr_init_ext_addr = (0 in set_ddr_init_ext_addr()
1878 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_4() argument
1908 ddr->timing_cfg_4 = (0 in set_timing_cfg_4()
1916 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4); in set_timing_cfg_4()
1920 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency) in set_timing_cfg_5() argument
1928 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + in set_timing_cfg_5()
1929 ((ddr->timing_cfg_2 & 0x00040000) >> 14); in set_timing_cfg_5()
1938 ddr->timing_cfg_5 = (0 in set_timing_cfg_5()
1944 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5); in set_timing_cfg_5()
1948 static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr) in set_timing_cfg_6() argument
1956 ddr->timing_cfg_6 = (0 in set_timing_cfg_6()
1963 debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6); in set_timing_cfg_6()
1967 fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_7() argument
1978 if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { in set_timing_cfg_7()
2011 ddr->timing_cfg_7 = (0 in set_timing_cfg_7()
2018 debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7); in set_timing_cfg_7()
2022 fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_8() argument
2030 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + in set_timing_cfg_8()
2031 ((ddr->timing_cfg_2 & 0x00040000) >> 14); in set_timing_cfg_8()
2060 ddr->timing_cfg_8 = (0 in set_timing_cfg_8()
2070 debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8); in set_timing_cfg_8()
2073 static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr) in set_timing_cfg_9() argument
2075 ddr->timing_cfg_9 = 0; in set_timing_cfg_9()
2076 debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9); in set_timing_cfg_9()
2080 static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr, in set_ddr_dq_mapping() argument
2083 unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1; in set_ddr_dq_mapping()
2095 ddr->dq_map_0 = ((dimm_params[i].dq_mapping[0] & 0x3F) << 26) | in set_ddr_dq_mapping()
2101 ddr->dq_map_1 = ((dimm_params[i].dq_mapping[5] & 0x3F) << 26) | in set_ddr_dq_mapping()
2107 ddr->dq_map_2 = ((dimm_params[i].dq_mapping[12] & 0x3F) << 26) | in set_ddr_dq_mapping()
2114 ddr->dq_map_3 = ((dimm_params[i].dq_mapping[17] & 0x3F) << 26) | in set_ddr_dq_mapping()
2120 debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0); in set_ddr_dq_mapping()
2121 debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1); in set_ddr_dq_mapping()
2122 debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2); in set_ddr_dq_mapping()
2123 debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3); in set_ddr_dq_mapping()
2125 static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_cfg_3() argument
2132 ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16; in set_ddr_sdram_cfg_3()
2134 debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3); in set_ddr_sdram_cfg_3()
2139 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) in set_ddr_zq_cntl() argument
2163 ddr->ddr_zq_cntl = (0 in set_ddr_zq_cntl()
2172 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl); in set_ddr_zq_cntl()
2176 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, in set_ddr_wrlvl_cntl() argument
2232 ddr->ddr_wrlvl_cntl = (0 in set_ddr_wrlvl_cntl()
2241 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl); in set_ddr_wrlvl_cntl()
2242 ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2; in set_ddr_wrlvl_cntl()
2243 debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2); in set_ddr_wrlvl_cntl()
2244 ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3; in set_ddr_wrlvl_cntl()
2245 debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3); in set_ddr_wrlvl_cntl()
2250 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it) in set_ddr_sr_cntr() argument
2253 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16; in set_ddr_sr_cntr()
2256 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) in set_ddr_eor() argument
2259 ddr->ddr_eor = 0x40000000; /* address hash enable */ in set_ddr_eor()
2264 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) in set_ddr_cdr1() argument
2266 ddr->ddr_cdr1 = popts->ddr_cdr1; in set_ddr_cdr1()
2267 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1); in set_ddr_cdr1()
2270 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) in set_ddr_cdr2() argument
2272 ddr->ddr_cdr2 = popts->ddr_cdr2; in set_ddr_cdr2()
2273 debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2); in set_ddr_cdr2()
2277 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) in check_fsl_memctl_config_regs() argument
2285 if (ddr->ddr_sdram_cfg & 0x10000000 in check_fsl_memctl_config_regs()
2286 && ddr->ddr_sdram_cfg & 0x00008000) { in check_fsl_memctl_config_regs()
2298 fsl_ddr_cfg_regs_t *ddr, in compute_fsl_memctl_config_regs() argument
2346 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t)); in compute_fsl_memctl_config_regs()
2477 ddr->cs[i].bnds = (0 in compute_fsl_memctl_config_regs()
2483 ddr->cs[i].bnds = 0xffffffff; in compute_fsl_memctl_config_regs()
2486 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds); in compute_fsl_memctl_config_regs()
2487 set_csn_config(dimm_number, i, ddr, popts, dimm_params); in compute_fsl_memctl_config_regs()
2488 set_csn_config_2(i, ddr); in compute_fsl_memctl_config_regs()
2498 set_ddr_eor(ddr, popts); in compute_fsl_memctl_config_regs()
2501 set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params); in compute_fsl_memctl_config_regs()
2504 set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency, in compute_fsl_memctl_config_regs()
2506 set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency); in compute_fsl_memctl_config_regs()
2507 set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm, in compute_fsl_memctl_config_regs()
2510 set_ddr_cdr1(ddr, popts); in compute_fsl_memctl_config_regs()
2511 set_ddr_cdr2(ddr, popts); in compute_fsl_memctl_config_regs()
2512 set_ddr_sdram_cfg(ddr, popts, common_dimm); in compute_fsl_memctl_config_regs()
2518 ddr->debug[18] = popts->cswl_override; in compute_fsl_memctl_config_regs()
2520 set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en); in compute_fsl_memctl_config_regs()
2521 set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm, in compute_fsl_memctl_config_regs()
2523 set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en); in compute_fsl_memctl_config_regs()
2525 set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en); in compute_fsl_memctl_config_regs()
2526 set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en); in compute_fsl_memctl_config_regs()
2528 set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm); in compute_fsl_memctl_config_regs()
2529 set_ddr_data_init(ddr); in compute_fsl_memctl_config_regs()
2530 set_ddr_sdram_clk_cntl(ddr, popts); in compute_fsl_memctl_config_regs()
2531 set_ddr_init_addr(ddr); in compute_fsl_memctl_config_regs()
2532 set_ddr_init_ext_addr(ddr); in compute_fsl_memctl_config_regs()
2533 set_timing_cfg_4(ddr, popts); in compute_fsl_memctl_config_regs()
2534 set_timing_cfg_5(ddr, cas_latency); in compute_fsl_memctl_config_regs()
2536 set_ddr_sdram_cfg_3(ddr, popts); in compute_fsl_memctl_config_regs()
2537 set_timing_cfg_6(ddr); in compute_fsl_memctl_config_regs()
2538 set_timing_cfg_7(ctrl_num, ddr, common_dimm); in compute_fsl_memctl_config_regs()
2539 set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency); in compute_fsl_memctl_config_regs()
2540 set_timing_cfg_9(ddr); in compute_fsl_memctl_config_regs()
2541 set_ddr_dq_mapping(ddr, dimm_params); in compute_fsl_memctl_config_regs()
2544 set_ddr_zq_cntl(ddr, zq_en); in compute_fsl_memctl_config_regs()
2545 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts); in compute_fsl_memctl_config_regs()
2547 set_ddr_sr_cntr(ddr, sr_it); in compute_fsl_memctl_config_regs()
2549 set_ddr_sdram_rcw(ddr, popts, common_dimm); in compute_fsl_memctl_config_regs()
2553 ddr->debug[2] = 0x00000400; in compute_fsl_memctl_config_regs()
2554 ddr->debug[4] = 0xff800800; in compute_fsl_memctl_config_regs()
2555 ddr->debug[5] = 0x08000800; in compute_fsl_memctl_config_regs()
2556 ddr->debug[6] = 0x08000800; in compute_fsl_memctl_config_regs()
2557 ddr->debug[7] = 0x08000800; in compute_fsl_memctl_config_regs()
2558 ddr->debug[8] = 0x08000800; in compute_fsl_memctl_config_regs()
2562 ddr->debug[2] |= 0x00000200; /* set bit 22 */ in compute_fsl_memctl_config_regs()
2570 if (IS_ACC_ECC_EN(ddr->ddr_sdram_cfg) || in compute_fsl_memctl_config_regs()
2571 IS_DBI(ddr->ddr_sdram_cfg_3)) { in compute_fsl_memctl_config_regs()
2572 ddr->debug[28] = ddr_in32(&ddrc->debug[28]); in compute_fsl_memctl_config_regs()
2573 ddr->debug[28] |= (0x9 << 20); in compute_fsl_memctl_config_regs()
2580 ddr->debug[28] |= ddr_in32(&ddrc->debug[28]); in compute_fsl_memctl_config_regs()
2581 ddr->debug[28] &= 0xff0fff00; in compute_fsl_memctl_config_regs()
2583 ddr->debug[28] |= 0x0080006a; in compute_fsl_memctl_config_regs()
2585 ddr->debug[28] |= 0x0070006f; in compute_fsl_memctl_config_regs()
2587 ddr->debug[28] |= 0x00700076; in compute_fsl_memctl_config_regs()
2589 ddr->debug[28] |= 0x0060007b; in compute_fsl_memctl_config_regs()
2591 ddr->debug[28] = (ddr->debug[28] & 0xffffff00) | in compute_fsl_memctl_config_regs()
2595 return check_fsl_memctl_config_regs(ddr); in compute_fsl_memctl_config_regs()
2607 struct ccsr_ddr __iomem *ddr = in erratum_a009942_check_cpo() local
2610 u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24; in erratum_a009942_check_cpo()
2615 sdram_cfg = ddr_in32(&ddr->sdram_cfg); in erratum_a009942_check_cpo()
2628 cpo = ddr_in32(&ddr->debug[i]); in erratum_a009942_check_cpo()
2640 cpo = ddr_in32(&ddr->debug[13]); in erratum_a009942_check_cpo()
2648 cpo_target = ddr_in32(&ddr->debug[28]) & 0xff; in erratum_a009942_check_cpo()