Lines Matching refs:misccfg
36 const struct socfpga_sdram_misc_config *misccfg; variable
775 afi_clocks = DIV_ROUND_UP(clocks, misccfg->afi_rate_ratio); in delay_for_n_mem_clocks()
968 rw_mgr_mem_init_load_regs(misccfg->tinit_cntr0_val, in rw_mgr_mem_initialize()
969 misccfg->tinit_cntr1_val, in rw_mgr_mem_initialize()
970 misccfg->tinit_cntr2_val, in rw_mgr_mem_initialize()
990 rw_mgr_mem_init_load_regs(misccfg->treset_cntr0_val, in rw_mgr_mem_initialize()
991 misccfg->treset_cntr1_val, in rw_mgr_mem_initialize()
992 misccfg->treset_cntr2_val, in rw_mgr_mem_initialize()
1033 misccfg->enable_super_quick_calibration; in rw_mgr_mem_calibrate_write_test_issue()
1376 misccfg->enable_super_quick_calibration); in rw_mgr_mem_calibrate_read_test()
1511 for (i = 0; i < misccfg->read_valid_fifo_size - 1; i++) in rw_mgr_decr_vfifo()
1525 for (v = 0; v < misccfg->read_valid_fifo_size; v++) { in find_vfifo_failing_read()
1597 const u32 end = misccfg->read_valid_fifo_size + (working ? 0 : 1); in sdr_find_phase()
1780 for (i = 0; i < misccfg->read_valid_fifo_size; i++) { in sdr_find_window_center()
3178 const u32 max_latency = (1 << misccfg->max_latency_count_width) - 1; in mem_init_latency()
3282 vfifo_offset = misccfg->calib_vfifo_offset; in mem_skip_calibrate()
3291 gbl->curr_read_lat = misccfg->calib_lfifo_offset; in mem_skip_calibrate()
3606 writel(misccfg->reg_file_init_seq_signature, &sdr_reg_file->signature); in initialize_reg_file()
3723 misccfg = socfpga_get_sdram_misc_config(); in sdram_calibration_full()