Lines Matching +full:timeout +full:- +full:sec
2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
19 #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
35 (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
41 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); in start_jr0() local
42 u32 ctpr_ms = sec_in32(&sec->ctpr_ms); in start_jr0()
43 u32 scfgr = sec_in32(&sec->scfgr); in start_jr0()
51 sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0); in start_jr0()
55 sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0); in start_jr0()
61 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); in jr_reset_liodn() local
62 sec_out32(&sec->jrliodnr[0].ls, 0); in jr_reset_liodn()
68 uint32_t jrcfg = sec_in32(®s->jrcfg1); in jr_disable_irq()
72 sec_out32(®s->jrcfg1, jrcfg); in jr_disable_irq()
79 phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring); in jr_initregs()
80 phys_addr_t op_base = virt_to_phys((void *)jr->output_ring); in jr_initregs()
83 sec_out32(®s->irba_h, ip_base >> 32); in jr_initregs()
85 sec_out32(®s->irba_h, 0x0); in jr_initregs()
87 sec_out32(®s->irba_l, (uint32_t)ip_base); in jr_initregs()
89 sec_out32(®s->orba_h, op_base >> 32); in jr_initregs()
91 sec_out32(®s->orba_h, 0x0); in jr_initregs()
93 sec_out32(®s->orba_l, (uint32_t)op_base); in jr_initregs()
94 sec_out32(®s->ors, JR_SIZE); in jr_initregs()
95 sec_out32(®s->irs, JR_SIZE); in jr_initregs()
97 if (!jr->irq) in jr_initregs()
107 jr->jq_id = DEFAULT_JR_ID; in jr_init()
108 jr->irq = DEFAULT_IRQ; in jr_init()
111 jr->liodn = DEFAULT_JR_LIODN; in jr_init()
113 jr->size = JR_SIZE; in jr_init()
114 jr->input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN, in jr_init()
116 if (!jr->input_ring) in jr_init()
117 return -1; in jr_init()
119 jr->op_size = roundup(JR_SIZE * sizeof(struct op_ring), in jr_init()
121 jr->output_ring = in jr_init()
122 (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr->op_size); in jr_init()
123 if (!jr->output_ring) in jr_init()
124 return -1; in jr_init()
126 memset(jr->input_ring, 0, JR_SIZE * sizeof(dma_addr_t)); in jr_init()
127 memset(jr->output_ring, 0, jr->op_size); in jr_init()
140 jr->head = 0; in jr_sw_cleanup()
141 jr->tail = 0; in jr_sw_cleanup()
142 jr->read_idx = 0; in jr_sw_cleanup()
143 jr->write_idx = 0; in jr_sw_cleanup()
144 memset(jr->info, 0, sizeof(jr->info)); in jr_sw_cleanup()
145 memset(jr->input_ring, 0, jr->size * sizeof(dma_addr_t)); in jr_sw_cleanup()
146 memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring)); in jr_sw_cleanup()
154 uint32_t timeout = 100000; in jr_hw_reset() local
157 sec_out32(®s->jrcr, JRCR_RESET); in jr_hw_reset()
159 jrint = sec_in32(®s->jrint); in jr_hw_reset()
161 JRINT_ERR_HALT_INPROGRESS) && --timeout); in jr_hw_reset()
163 jrint = sec_in32(®s->jrint); in jr_hw_reset()
165 JRINT_ERR_HALT_INPROGRESS) && timeout == 0) in jr_hw_reset()
166 return -1; in jr_hw_reset()
168 timeout = 100000; in jr_hw_reset()
169 sec_out32(®s->jrcr, JRCR_RESET); in jr_hw_reset()
171 jrcr = sec_in32(®s->jrcr); in jr_hw_reset()
172 } while ((jrcr & JRCR_RESET) && --timeout); in jr_hw_reset()
174 if (timeout == 0) in jr_hw_reset()
175 return -1; in jr_hw_reset()
180 /* -1 --- error, can't enqueue -- no space available */
187 int head = jr->head; in jr_enqueue()
195 /* The descriptor must be submitted to SEC block as per endianness in jr_enqueue()
196 * of the SEC Block. in jr_enqueue()
197 * So, if the endianness of Core and SEC block is different, each word in jr_enqueue()
198 * of the descriptor will be byte-swapped. in jr_enqueue()
207 jr->info[head].desc_phys_addr = desc_phys_addr; in jr_enqueue()
208 jr->info[head].callback = (void *)callback; in jr_enqueue()
209 jr->info[head].arg = arg; in jr_enqueue()
210 jr->info[head].op_done = 0; in jr_enqueue()
212 unsigned long start = (unsigned long)&jr->info[head] & in jr_enqueue()
213 ~(ARCH_DMA_MINALIGN - 1); in jr_enqueue()
214 unsigned long end = ALIGN((unsigned long)&jr->info[head] + in jr_enqueue()
221 * depend on endianness of SEC block. in jr_enqueue()
224 addr_lo = (uint32_t *)(&jr->input_ring[head]); in jr_enqueue()
225 addr_hi = (uint32_t *)(&jr->input_ring[head]) + 1; in jr_enqueue()
227 addr_hi = (uint32_t *)(&jr->input_ring[head]); in jr_enqueue()
228 addr_lo = (uint32_t *)(&jr->input_ring[head]) + 1; in jr_enqueue()
236 sec_out32(&jr->input_ring[head], desc_phys_addr); in jr_enqueue()
239 start = (unsigned long)&jr->input_ring[head] & ~(ARCH_DMA_MINALIGN - 1); in jr_enqueue()
240 end = ALIGN((unsigned long)&jr->input_ring[head] + in jr_enqueue()
244 jr->head = (head + 1) & (jr->size - 1); in jr_enqueue()
247 start = (unsigned long)jr->output_ring & in jr_enqueue()
248 ~(ARCH_DMA_MINALIGN - 1); in jr_enqueue()
249 end = ALIGN((unsigned long)jr->output_ring + jr->op_size, in jr_enqueue()
253 sec_out32(®s->irja, 1); in jr_enqueue()
262 int head = jr->head; in jr_dequeue()
263 int tail = jr->tail; in jr_dequeue()
273 while (sec_in32(®s->orsf) && CIRC_CNT(jr->head, jr->tail, in jr_dequeue()
274 jr->size)) { in jr_dequeue()
282 * depend on endianness of SEC block. in jr_dequeue()
285 addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc); in jr_dequeue()
286 addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1; in jr_dequeue()
288 addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc); in jr_dequeue()
289 addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1; in jr_dequeue()
297 addr = (uint32_t *)&jr->output_ring[jr->tail].desc; in jr_dequeue()
301 uint32_t status = sec_in32(&jr->output_ring[jr->tail].status); in jr_dequeue()
303 for (i = 0; CIRC_CNT(head, tail + i, jr->size) >= 1; i++) { in jr_dequeue()
304 idx = (tail + i) & (jr->size - 1); in jr_dequeue()
305 if (op_desc == jr->info[idx].desc_phys_addr) { in jr_dequeue()
313 return -1; in jr_dequeue()
315 jr->info[idx].op_done = 1; in jr_dequeue()
316 callback = (void *)jr->info[idx].callback; in jr_dequeue()
317 arg = jr->info[idx].arg; in jr_dequeue()
325 tail = (tail + 1) & (jr->size - 1); in jr_dequeue()
326 } while (jr->info[tail].op_done); in jr_dequeue()
328 jr->tail = tail; in jr_dequeue()
329 jr->read_idx = (jr->read_idx + 1) & (jr->size - 1); in jr_dequeue()
331 sec_out32(®s->orjr, 1); in jr_dequeue()
332 jr->info[idx].op_done = 0; in jr_dequeue()
343 x->status = status; in desc_done()
347 x->done = 1; in desc_done()
353 unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT); in run_descriptor_jr_idx() local
361 debug("Error in SEC enq\n"); in run_descriptor_jr_idx()
367 timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT); in run_descriptor_jr_idx()
371 debug("Error in SEC deq\n"); in run_descriptor_jr_idx()
376 if ((get_ticks() - timeval) > timeout) { in run_descriptor_jr_idx()
377 debug("SEC Dequeue timed out\n"); in run_descriptor_jr_idx()
399 return -1; in jr_reset_sec()
414 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); in sec_reset_idx() local
415 uint32_t mcfgr = sec_in32(&sec->mcfgr); in sec_reset_idx()
416 uint32_t timeout = 100000; in sec_reset_idx() local
419 sec_out32(&sec->mcfgr, mcfgr); in sec_reset_idx()
422 sec_out32(&sec->mcfgr, mcfgr); in sec_reset_idx()
424 mcfgr = sec_in32(&sec->mcfgr); in sec_reset_idx()
425 } while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout); in sec_reset_idx()
427 if (timeout == 0) in sec_reset_idx()
428 return -1; in sec_reset_idx()
430 timeout = 100000; in sec_reset_idx()
432 mcfgr = sec_in32(&sec->mcfgr); in sec_reset_idx()
433 } while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout); in sec_reset_idx()
435 if (timeout == 0) in sec_reset_idx()
436 return -1; in sec_reset_idx()
451 ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx); in instantiate_rng() local
453 (struct rng4tst __iomem *)&sec->rng; in instantiate_rng()
460 return -1; in instantiate_rng()
473 rdsta_val = sec_in32(&rng->rdsta); in instantiate_rng()
475 return -1; in instantiate_rng()
482 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); in get_rng_vid() local
483 u32 cha_vid = sec_in32(&sec->chavid_ls); in get_rng_vid()
494 ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx); in kick_trng() local
496 (struct rng4tst __iomem *)&sec->rng; in kick_trng()
500 sec_setbits32(&rng->rtmctl, RTMCTL_PRGM); in kick_trng()
501 /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the in kick_trng()
504 val = sec_in32(&rng->rtsdctl); in kick_trng()
507 sec_out32(&rng->rtsdctl, val); in kick_trng()
509 sec_out32(&rng->rtfreqmin, ent_delay >> 2); in kick_trng()
511 sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE); in kick_trng()
516 sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC); in kick_trng()
518 sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM); in kick_trng()
524 ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx); in rng_init() local
526 (struct rng4tst __iomem *)&sec->rng; in rng_init()
528 u32 rdsta = sec_in32(&rng->rdsta); in rng_init()
553 } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); in rng_init()
560 sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE); in rng_init()
567 ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); in sec_init_idx() local
568 uint32_t mcr = sec_in32(&sec->mcfgr); in sec_init_idx()
578 printf("SEC initialization failed\n"); in sec_init_idx()
579 return -1; in sec_init_idx()
585 * For AXI Write - Cacheable, Write Back, Write allocate in sec_init_idx()
586 * For AXI Read - Cacheable, Read allocate in sec_init_idx()
599 sec_out32(&sec->mcfgr, mcr); in sec_init_idx()
604 * For SPL Build, Set the Liodns in SEC JR0 for in sec_init_idx()
611 liodnr = sec_in32(&sec->jrliodnr[0].ls) & in sec_init_idx()
616 sec_out32(&sec->jrliodnr[0].ls, liodnr); in sec_init_idx()
618 liodnr = sec_in32(&sec->jrliodnr[0].ls); in sec_init_idx()
626 printf("SEC initialization failed\n"); in sec_init_idx()
627 return -1; in sec_init_idx()
633 return -1; in sec_init_idx()
640 printf("SEC%u: RNG instantiation failed\n", sec_idx); in sec_init_idx()
641 return -1; in sec_init_idx()
643 printf("SEC%u: RNG instantiated\n", sec_idx); in sec_init_idx()