633 			parent = priv->cpll_hz;  in rv1126_pdbus_get_clk()
644 			parent = priv->cpll_hz;  in rv1126_pdbus_get_clk()
656 			parent = priv->cpll_hz;  in rv1126_pdbus_get_clk()
679 			src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rv1126_pdbus_set_clk()
952 			parent = priv->cpll_hz;  in rv1126_crypto_get_clk()
963 			parent = priv->cpll_hz;  in rv1126_crypto_get_clk()
974 			parent = priv->cpll_hz;  in rv1126_crypto_get_clk()
1053 		return DIV_TO_RATE(priv->cpll_hz, div) / 2;  in rv1126_mmc_get_clk()
1116 		parent = priv->cpll_hz;  in rv1126_sfc_get_clk()
1148 		parent = priv->cpll_hz;  in rv1126_nand_get_clk()
1180 		parent = priv->cpll_hz;  in rv1126_aclk_vop_get_clk()
1213 		parent = priv->cpll_hz;  in rv1126_dclk_vop_get_clk()
1232 			pll_rate = priv->cpll_hz;  in rv1126_dclk_vop_set_clk()
1277 		parent = priv->cpll_hz;  in rv1126_scr1_get_clk()
1308 		parent = priv->cpll_hz;  in rv1126_gmac_src_get_clk()
1322 	src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rv1126_gmac_src_set_clk()
1341 		parent = priv->cpll_hz;  in rv1126_gmac_out_get_clk()
1355 	src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rv1126_gmac_out_set_clk()
1482 		parent = priv->cpll_hz;  in rv1126_clk_pdvi_ispp_get_clk()
1511 	if (!(priv->cpll_hz % rate)) {  in rv1126_clk_pdvi_ispp_set_clk()
1512 		parent = priv->cpll_hz;  in rv1126_clk_pdvi_ispp_set_clk()
1543 		parent = priv->cpll_hz;  in rv1126_clk_isp_get_clk()
1557 	if (!(priv->cpll_hz % rate)) {  in rv1126_clk_isp_set_clk()
1558 		parent = priv->cpll_hz;  in rv1126_clk_isp_set_clk()
1590 		parent = priv->cpll_hz;  in rv1126_dclk_decom_get_clk()
2146 	if (priv->cpll_hz != CPLL_HZ) {  in rv1126_clk_init()
2150 			priv->cpll_hz = CPLL_HZ;  in rv1126_clk_init()