Lines Matching full:rate
25 .rate = _rate##U, \
99 ulong rate);
157 static ulong rv1126_gpll_set_pmuclk(struct rv1126_pmuclk_priv *pmu_priv, ulong rate) in rv1126_gpll_set_pmuclk() argument
172 if (rv1126_gpll_set_rate(priv, pmu_priv, rate)) { in rv1126_gpll_set_pmuclk()
173 printf("%s: failed to set gpll rate %lu\n", __func__, rate); in rv1126_gpll_set_pmuclk()
195 ulong rate) in rv1126_rtc32k_set_pmuclk() argument
203 rational_best_approximation(rate, OSC_HZ, in rv1126_rtc32k_set_pmuclk()
236 ulong clk_id, ulong rate) in rv1126_i2c_set_pmuclk() argument
241 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_i2c_set_pmuclk()
289 ulong clk_id, ulong rate) in rv1126_pwm_set_pmuclk() argument
296 if (rate == OSC_HZ) { in rv1126_pwm_set_pmuclk()
303 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pwm_set_pmuclk()
314 if (rate == OSC_HZ) { in rv1126_pwm_set_pmuclk()
321 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pwm_set_pmuclk()
350 ulong rate) in rv1126_spi_set_pmuclk() argument
355 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_spi_set_pmuclk()
378 ulong rate) in rv1126_pdpmu_set_pmuclk() argument
383 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdpmu_set_pmuclk()
396 ulong rate = 0; in rv1126_pmuclk_get_rate() local
406 rate = rv1126_gpll_get_pmuclk(priv); in rv1126_pmuclk_get_rate()
409 rate = rv1126_rtc32k_get_pmuclk(priv); in rv1126_pmuclk_get_rate()
413 rate = rv1126_i2c_get_pmuclk(priv, clk->id); in rv1126_pmuclk_get_rate()
417 rate = rv1126_pwm_get_pmuclk(priv, clk->id); in rv1126_pmuclk_get_rate()
420 rate = rv1126_spi_get_pmuclk(priv); in rv1126_pmuclk_get_rate()
423 rate = rv1126_pdpmu_get_pmuclk(priv); in rv1126_pmuclk_get_rate()
429 return rate; in rv1126_pmuclk_get_rate()
432 static ulong rv1126_pmuclk_set_rate(struct clk *clk, ulong rate) in rv1126_pmuclk_set_rate() argument
442 debug("%s %ld %ld\n", __func__, clk->id, rate); in rv1126_pmuclk_set_rate()
445 ret = rv1126_gpll_set_pmuclk(priv, rate); in rv1126_pmuclk_set_rate()
448 ret = rv1126_rtc32k_set_pmuclk(priv, rate); in rv1126_pmuclk_set_rate()
452 ret = rv1126_i2c_set_pmuclk(priv, clk->id, rate); in rv1126_pmuclk_set_rate()
456 ret = rv1126_pwm_set_pmuclk(priv, clk->id, rate); in rv1126_pmuclk_set_rate()
459 ret = rv1126_spi_set_pmuclk(priv, rate); in rv1126_pmuclk_set_rate()
462 ret = rv1126_pdpmu_set_pmuclk(priv, rate); in rv1126_pmuclk_set_rate()
561 const struct rockchip_cpu_rate_table *rate; in rv1126_armclk_set_clk() local
564 rate = rockchip_get_cpu_settings(rv1126_cpu_rates, hz); in rv1126_armclk_set_clk()
565 if (!rate) { in rv1126_armclk_set_clk()
566 printf("%s unsupported rate\n", __func__); in rv1126_armclk_set_clk()
581 rate->pclk_div << CORE_DBG_DIV_SHIFT | in rv1126_armclk_set_clk()
582 rate->aclk_div << CORE_ACLK_DIV_SHIFT); in rv1126_armclk_set_clk()
586 rate->pclk_div << CORE_DBG_DIV_SHIFT | in rv1126_armclk_set_clk()
587 rate->aclk_div << CORE_ACLK_DIV_SHIFT); in rv1126_armclk_set_clk()
607 static ulong rv1126_pdcore_set_clk(struct rv1126_clk_priv *priv, ulong rate) in rv1126_pdcore_set_clk() argument
611 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdcore_set_clk()
668 ulong rate) in rv1126_pdbus_set_clk() argument
675 if (CPLL_HZ % rate) { in rv1126_pdbus_set_clk()
676 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdbus_set_clk()
679 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rv1126_pdbus_set_clk()
689 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdbus_set_clk()
698 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdbus_set_clk()
738 ulong rate) in rv1126_pdphp_set_clk() argument
743 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdphp_set_clk()
777 static ulong rv1126_pdaudio_set_clk(struct rv1126_clk_priv *priv, ulong rate) in rv1126_pdaudio_set_clk() argument
782 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdaudio_set_clk()
821 ulong rate) in rv1126_i2c_set_clk() argument
826 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_i2c_set_clk()
864 static ulong rv1126_spi_set_clk(struct rv1126_clk_priv *priv, ulong rate) in rv1126_spi_set_clk() argument
869 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_spi_set_clk()
894 static ulong rv1126_pwm_set_clk(struct rv1126_clk_priv *priv, ulong rate) in rv1126_pwm_set_clk() argument
899 if (rate == OSC_HZ) { in rv1126_pwm_set_clk()
904 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pwm_set_clk()
926 static ulong rv1126_saradc_set_clk(struct rv1126_clk_priv *priv, ulong rate) in rv1126_saradc_set_clk() argument
931 src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); in rv1126_saradc_set_clk()
986 ulong rate) in rv1126_crypto_set_clk() argument
991 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_crypto_set_clk()
1061 ulong rate) in rv1126_mmc_set_clk() argument
1086 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, rate); in rv1126_mmc_set_clk()
1090 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, rate); in rv1126_mmc_set_clk()
1123 static ulong rv1126_sfc_set_clk(struct rv1126_clk_priv *priv, ulong rate) in rv1126_sfc_set_clk() argument
1128 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_sfc_set_clk()
1155 static ulong rv1126_nand_set_clk(struct rv1126_clk_priv *priv, ulong rate) in rv1126_nand_set_clk() argument
1160 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_nand_set_clk()
1187 static ulong rv1126_aclk_vop_set_clk(struct rv1126_clk_priv *priv, ulong rate) in rv1126_aclk_vop_set_clk() argument
1192 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_aclk_vop_set_clk()
1220 static ulong rv1126_dclk_vop_set_clk(struct rv1126_clk_priv *priv, ulong rate) in rv1126_dclk_vop_set_clk() argument
1239 div = DIV_ROUND_UP(pll_rate, rate); in rv1126_dclk_vop_set_clk()
1243 if (abs(rate - now) < abs(rate - best_rate)) { in rv1126_dclk_vop_set_clk()
1258 printf("do not support this vop freq %lu\n", rate); in rv1126_dclk_vop_set_clk()
1284 static ulong rv1126_scr1_set_clk(struct rv1126_clk_priv *priv, ulong rate) in rv1126_scr1_set_clk() argument
1289 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_scr1_set_clk()
1317 static ulong rv1126_gmac_src_set_clk(struct rv1126_clk_priv *priv, ulong rate) in rv1126_gmac_src_set_clk() argument
1322 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rv1126_gmac_src_set_clk()
1350 static ulong rv1126_gmac_out_set_clk(struct rv1126_clk_priv *priv, ulong rate) in rv1126_gmac_out_set_clk() argument
1355 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rv1126_gmac_out_set_clk()
1365 static ulong rv1126_gmac_tx_rx_set_clk(struct rv1126_clk_priv *priv, ulong rate) in rv1126_gmac_tx_rx_set_clk() argument
1374 if (rate == 2500000) in rv1126_gmac_tx_rx_set_clk()
1376 else if (rate == 25000000) in rv1126_gmac_tx_rx_set_clk()
1383 if (rate == 2500000) in rv1126_gmac_tx_rx_set_clk()
1430 ulong rate) in rv1126_clk_mipicsi_out_set_clk() argument
1434 if (rate == OSC_HZ) { in rv1126_clk_mipicsi_out_set_clk()
1437 } else if (rate == 27000000) { in rv1126_clk_mipicsi_out_set_clk()
1445 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_clk_mipicsi_out_set_clk()
1492 ulong clk_id, ulong rate) in rv1126_clk_pdvi_ispp_set_clk() argument
1511 if (!(priv->cpll_hz % rate)) { in rv1126_clk_pdvi_ispp_set_clk()
1514 } else if (!(priv->hpll_hz % rate)) { in rv1126_clk_pdvi_ispp_set_clk()
1522 src_clk_div = DIV_ROUND_UP(parent, rate); in rv1126_clk_pdvi_ispp_set_clk()
1552 static ulong rv1126_clk_isp_set_clk(struct rv1126_clk_priv *priv, ulong rate) in rv1126_clk_isp_set_clk() argument
1557 if (!(priv->cpll_hz % rate)) { in rv1126_clk_isp_set_clk()
1560 } else if (!(priv->hpll_hz % rate)) { in rv1126_clk_isp_set_clk()
1568 src_clk_div = DIV_ROUND_UP(parent, rate); in rv1126_clk_isp_set_clk()
1597 static ulong rv1126_dclk_decom_set_clk(struct rv1126_clk_priv *priv, ulong rate) in rv1126_dclk_decom_set_clk() argument
1602 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_dclk_decom_set_clk()
1615 ulong rate = 0; in rv1126_clk_get_rate() local
1625 rate = rockchip_pll_get_rate(&rv1126_pll_clks[APLL], priv->cru, in rv1126_clk_get_rate()
1629 rate = rockchip_pll_get_rate(&rv1126_pll_clks[CPLL], priv->cru, in rv1126_clk_get_rate()
1633 rate = rockchip_pll_get_rate(&rv1126_pll_clks[HPLL], priv->cru, in rv1126_clk_get_rate()
1637 rate = rockchip_pll_get_rate(&rv1126_pll_clks[DPLL], priv->cru, in rv1126_clk_get_rate()
1641 rate = rv1126_pdcore_get_clk(priv); in rv1126_clk_get_rate()
1647 rate = rv1126_pdbus_get_clk(priv, clk->id); in rv1126_clk_get_rate()
1651 rate = rv1126_pdphp_get_clk(priv, clk->id); in rv1126_clk_get_rate()
1654 rate = rv1126_pdaudio_get_clk(priv); in rv1126_clk_get_rate()
1660 rate = rv1126_i2c_get_clk(priv, clk->id); in rv1126_clk_get_rate()
1663 rate = rv1126_spi_get_clk(priv); in rv1126_clk_get_rate()
1666 rate = rv1126_pwm_get_clk(priv); in rv1126_clk_get_rate()
1669 rate = rv1126_saradc_get_clk(priv); in rv1126_clk_get_rate()
1674 rate = rv1126_crypto_get_clk(priv, clk->id); in rv1126_clk_get_rate()
1683 rate = rv1126_mmc_get_clk(priv, clk->id); in rv1126_clk_get_rate()
1686 rate = rv1126_sfc_get_clk(priv); in rv1126_clk_get_rate()
1689 rate = rv1126_nand_get_clk(priv); in rv1126_clk_get_rate()
1693 rate = rv1126_aclk_vop_get_clk(priv); in rv1126_clk_get_rate()
1696 rate = rv1126_dclk_vop_get_clk(priv); in rv1126_clk_get_rate()
1699 rate = rv1126_scr1_get_clk(priv); in rv1126_clk_get_rate()
1702 rate = rv1126_gmac_src_get_clk(priv); in rv1126_clk_get_rate()
1705 rate = rv1126_gmac_out_get_clk(priv); in rv1126_clk_get_rate()
1708 rate = rv1126_pclk_gmac_get_clk(priv); in rv1126_clk_get_rate()
1712 rate = rv1126_clk_mipicsi_out_get_clk(priv); in rv1126_clk_get_rate()
1715 rate = rv1126_clk_isp_get_clk(priv); in rv1126_clk_get_rate()
1720 rate = rv1126_clk_pdvi_ispp_get_clk(priv, clk->id); in rv1126_clk_get_rate()
1724 rate = rv1126_dclk_decom_get_clk(priv); in rv1126_clk_get_rate()
1730 return rate; in rv1126_clk_get_rate()
1733 static ulong rv1126_clk_set_rate(struct clk *clk, ulong rate) in rv1126_clk_set_rate() argument
1747 rv1126_armclk_set_clk(priv, rate); in rv1126_clk_set_rate()
1748 priv->armclk_hz = rate; in rv1126_clk_set_rate()
1752 CPLL, rate); in rv1126_clk_set_rate()
1756 HPLL, rate); in rv1126_clk_set_rate()
1762 ret = rv1126_pdbus_set_clk(priv, clk->id, rate); in rv1126_clk_set_rate()
1766 ret = rv1126_pdphp_set_clk(priv, clk->id, rate); in rv1126_clk_set_rate()
1769 ret = rv1126_pdcore_set_clk(priv, rate); in rv1126_clk_set_rate()
1772 ret = rv1126_pdaudio_set_clk(priv, rate); in rv1126_clk_set_rate()
1778 ret = rv1126_i2c_set_clk(priv, clk->id, rate); in rv1126_clk_set_rate()
1781 ret = rv1126_spi_set_clk(priv, rate); in rv1126_clk_set_rate()
1784 ret = rv1126_pwm_set_clk(priv, rate); in rv1126_clk_set_rate()
1787 ret = rv1126_saradc_set_clk(priv, rate); in rv1126_clk_set_rate()
1792 ret = rv1126_crypto_set_clk(priv, clk->id, rate); in rv1126_clk_set_rate()
1800 ret = rv1126_mmc_set_clk(priv, clk->id, rate); in rv1126_clk_set_rate()
1803 ret = rv1126_sfc_set_clk(priv, rate); in rv1126_clk_set_rate()
1806 ret = rv1126_nand_set_clk(priv, rate); in rv1126_clk_set_rate()
1810 ret = rv1126_aclk_vop_set_clk(priv, rate); in rv1126_clk_set_rate()
1813 ret = rv1126_dclk_vop_set_clk(priv, rate); in rv1126_clk_set_rate()
1816 ret = rv1126_scr1_set_clk(priv, rate); in rv1126_clk_set_rate()
1819 ret = rv1126_gmac_src_set_clk(priv, rate); in rv1126_clk_set_rate()
1822 ret = rv1126_gmac_out_set_clk(priv, rate); in rv1126_clk_set_rate()
1825 ret = rv1126_gmac_tx_rx_set_clk(priv, rate); in rv1126_clk_set_rate()
1829 ret = rv1126_clk_mipicsi_out_set_clk(priv, rate); in rv1126_clk_set_rate()
1832 ret = rv1126_clk_isp_set_clk(priv, rate); in rv1126_clk_set_rate()
1837 ret = rv1126_clk_pdvi_ispp_set_clk(priv, clk->id, rate); in rv1126_clk_set_rate()
1841 ret = rv1126_dclk_decom_set_clk(priv, rate); in rv1126_clk_set_rate()
1868 ulong rate; in rv1126_mmc_get_phase() local
1870 rate = rv1126_clk_get_rate(clk); in rv1126_mmc_get_phase()
1871 if (rate < 0) in rv1126_mmc_get_phase()
1872 return rate; in rv1126_mmc_get_phase()
1887 36 * (rate / 1000000); in rv1126_mmc_get_phase()
1903 ulong rate; in rv1126_mmc_set_phase() local
1905 rate = rv1126_clk_get_rate(clk); in rv1126_mmc_set_phase()
1906 if (rate < 0) in rv1126_mmc_set_phase()
1907 return rate; in rv1126_mmc_set_phase()
1918 delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 * in rv1126_mmc_set_phase()
2069 ulong rate) in rv1126_gpll_set_rate() argument
2088 pmu_priv->pmucru, GPLL, rate)) in rv1126_gpll_set_rate()
2090 pmu_priv->gpll_hz = rate; in rv1126_gpll_set_rate()
2091 priv->gpll_hz = rate; in rv1126_gpll_set_rate()
2102 static int rv1126_gpll_set_clk(struct rv1126_clk_priv *priv, ulong rate) in rv1126_gpll_set_clk() argument
2118 if (rv1126_gpll_set_rate(priv, pmu_priv, rate)) { in rv1126_gpll_set_clk()
2119 printf("%s: failed to set gpll rate %lu\n", __func__, rate); in rv1126_gpll_set_clk()
2274 unsigned long rate; in soc_clk_dump() local
2311 rate = clk_get_rate(&clk); in soc_clk_dump()
2314 if (rate < 0) in soc_clk_dump()
2319 rate / 1000); in soc_clk_dump()
2321 if (rate < 0) in soc_clk_dump()
2326 rate / 1000); in soc_clk_dump()