Lines Matching +full:clk +full:- +full:div
1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Finley Xiao <finley.xiao@rock-chips.com>
9 #include <clk-uclass.h>
19 #include <dt-bindings/clock/rv1126-cru.h>
30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
103 * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
154 priv->pmucru, GPLL); in rv1126_gpll_get_pmuclk()
174 return -EINVAL; in rv1126_gpll_set_pmuclk()
181 struct rv1126_pmucru *pmucru = priv->pmucru; in rv1126_rtc32k_get_pmuclk()
185 fracdiv = readl(&pmucru->pmu_clksel_con[13]); in rv1126_rtc32k_get_pmuclk()
197 struct rv1126_pmucru *pmucru = priv->pmucru; in rv1126_rtc32k_set_pmuclk()
200 rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK, in rv1126_rtc32k_set_pmuclk()
204 GENMASK(16 - 1, 0), in rv1126_rtc32k_set_pmuclk()
205 GENMASK(16 - 1, 0), in rv1126_rtc32k_set_pmuclk()
208 writel(val, &pmucru->pmu_clksel_con[13]); in rv1126_rtc32k_set_pmuclk()
216 struct rv1126_pmucru *pmucru = priv->pmucru; in rv1126_i2c_get_pmuclk()
217 u32 div, con; in rv1126_i2c_get_pmuclk() local
221 con = readl(&pmucru->pmu_clksel_con[2]); in rv1126_i2c_get_pmuclk()
222 div = (con & CLK_I2C0_DIV_MASK) >> CLK_I2C0_DIV_SHIFT; in rv1126_i2c_get_pmuclk()
225 con = readl(&pmucru->pmu_clksel_con[3]); in rv1126_i2c_get_pmuclk()
226 div = (con & CLK_I2C1_DIV_MASK) >> CLK_I2C1_DIV_SHIFT; in rv1126_i2c_get_pmuclk()
229 return -ENOENT; in rv1126_i2c_get_pmuclk()
232 return DIV_TO_RATE(priv->gpll_hz, div); in rv1126_i2c_get_pmuclk()
238 struct rv1126_pmucru *pmucru = priv->pmucru; in rv1126_i2c_set_pmuclk()
241 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_i2c_set_pmuclk()
242 assert(src_clk_div - 1 <= 127); in rv1126_i2c_set_pmuclk()
246 rk_clrsetreg(&pmucru->pmu_clksel_con[2], CLK_I2C0_DIV_MASK, in rv1126_i2c_set_pmuclk()
247 (src_clk_div - 1) << CLK_I2C0_DIV_SHIFT); in rv1126_i2c_set_pmuclk()
250 rk_clrsetreg(&pmucru->pmu_clksel_con[3], CLK_I2C2_DIV_MASK, in rv1126_i2c_set_pmuclk()
251 (src_clk_div - 1) << CLK_I2C2_DIV_SHIFT); in rv1126_i2c_set_pmuclk()
254 return -ENOENT; in rv1126_i2c_set_pmuclk()
263 struct rv1126_pmucru *pmucru = priv->pmucru; in rv1126_pwm_get_pmuclk()
264 u32 div, sel, con; in rv1126_pwm_get_pmuclk() local
268 con = readl(&pmucru->pmu_clksel_con[6]); in rv1126_pwm_get_pmuclk()
270 div = (con & CLK_PWM0_DIV_MASK) >> CLK_PWM0_DIV_SHIFT; in rv1126_pwm_get_pmuclk()
275 con = readl(&pmucru->pmu_clksel_con[6]); in rv1126_pwm_get_pmuclk()
277 div = (con & CLK_PWM1_DIV_MASK) >> CLK_PWM1_DIV_SHIFT; in rv1126_pwm_get_pmuclk()
282 return -ENOENT; in rv1126_pwm_get_pmuclk()
285 return DIV_TO_RATE(priv->gpll_hz, div); in rv1126_pwm_get_pmuclk()
291 struct rv1126_pmucru *pmucru = priv->pmucru; in rv1126_pwm_set_pmuclk()
297 rk_clrsetreg(&pmucru->pmu_clksel_con[6], in rv1126_pwm_set_pmuclk()
300 rk_clrsetreg(&pmucru->pmu_clksel_con[6], in rv1126_pwm_set_pmuclk()
303 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pwm_set_pmuclk()
304 assert(src_clk_div - 1 <= 127); in rv1126_pwm_set_pmuclk()
305 rk_clrsetreg(&pmucru->pmu_clksel_con[6], in rv1126_pwm_set_pmuclk()
307 (src_clk_div - 1) << CLK_PWM0_DIV_SHIFT); in rv1126_pwm_set_pmuclk()
308 rk_clrsetreg(&pmucru->pmu_clksel_con[6], in rv1126_pwm_set_pmuclk()
315 rk_clrsetreg(&pmucru->pmu_clksel_con[6], in rv1126_pwm_set_pmuclk()
318 rk_clrsetreg(&pmucru->pmu_clksel_con[6], in rv1126_pwm_set_pmuclk()
321 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pwm_set_pmuclk()
322 assert(src_clk_div - 1 <= 127); in rv1126_pwm_set_pmuclk()
323 rk_clrsetreg(&pmucru->pmu_clksel_con[6], in rv1126_pwm_set_pmuclk()
325 (src_clk_div - 1) << CLK_PWM1_DIV_SHIFT); in rv1126_pwm_set_pmuclk()
326 rk_clrsetreg(&pmucru->pmu_clksel_con[6], in rv1126_pwm_set_pmuclk()
332 return -ENOENT; in rv1126_pwm_set_pmuclk()
340 struct rv1126_pmucru *pmucru = priv->pmucru; in rv1126_spi_get_pmuclk()
341 u32 div, con; in rv1126_spi_get_pmuclk() local
343 con = readl(&pmucru->pmu_clksel_con[9]); in rv1126_spi_get_pmuclk()
344 div = (con & CLK_SPI0_DIV_MASK) >> CLK_SPI0_DIV_SHIFT; in rv1126_spi_get_pmuclk()
346 return DIV_TO_RATE(priv->gpll_hz, div); in rv1126_spi_get_pmuclk()
352 struct rv1126_pmucru *pmucru = priv->pmucru; in rv1126_spi_set_pmuclk()
355 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_spi_set_pmuclk()
356 assert(src_clk_div - 1 <= 127); in rv1126_spi_set_pmuclk()
358 rk_clrsetreg(&pmucru->pmu_clksel_con[9], in rv1126_spi_set_pmuclk()
361 (src_clk_div - 1) << CLK_SPI0_DIV_SHIFT); in rv1126_spi_set_pmuclk()
368 struct rv1126_pmucru *pmucru = priv->pmucru; in rv1126_pdpmu_get_pmuclk()
369 u32 div, con; in rv1126_pdpmu_get_pmuclk() local
371 con = readl(&pmucru->pmu_clksel_con[1]); in rv1126_pdpmu_get_pmuclk()
372 div = (con & PCLK_PDPMU_DIV_MASK) >> PCLK_PDPMU_DIV_SHIFT; in rv1126_pdpmu_get_pmuclk()
374 return DIV_TO_RATE(priv->gpll_hz, div); in rv1126_pdpmu_get_pmuclk()
380 struct rv1126_pmucru *pmucru = priv->pmucru; in rv1126_pdpmu_set_pmuclk()
383 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdpmu_set_pmuclk()
384 assert(src_clk_div - 1 <= 31); in rv1126_pdpmu_set_pmuclk()
386 rk_clrsetreg(&pmucru->pmu_clksel_con[1], in rv1126_pdpmu_set_pmuclk()
388 (src_clk_div - 1) << PCLK_PDPMU_DIV_SHIFT); in rv1126_pdpmu_set_pmuclk()
393 static ulong rv1126_pmuclk_get_rate(struct clk *clk) in rv1126_pmuclk_get_rate() argument
395 struct rv1126_pmuclk_priv *priv = dev_get_priv(clk->dev); in rv1126_pmuclk_get_rate()
398 if (!priv->gpll_hz) { in rv1126_pmuclk_get_rate()
399 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); in rv1126_pmuclk_get_rate()
400 return -ENOENT; in rv1126_pmuclk_get_rate()
403 debug("%s %ld\n", __func__, clk->id); in rv1126_pmuclk_get_rate()
404 switch (clk->id) { in rv1126_pmuclk_get_rate()
413 rate = rv1126_i2c_get_pmuclk(priv, clk->id); in rv1126_pmuclk_get_rate()
417 rate = rv1126_pwm_get_pmuclk(priv, clk->id); in rv1126_pmuclk_get_rate()
426 return -ENOENT; in rv1126_pmuclk_get_rate()
432 static ulong rv1126_pmuclk_set_rate(struct clk *clk, ulong rate) in rv1126_pmuclk_set_rate() argument
434 struct rv1126_pmuclk_priv *priv = dev_get_priv(clk->dev); in rv1126_pmuclk_set_rate()
437 if (!priv->gpll_hz) { in rv1126_pmuclk_set_rate()
438 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); in rv1126_pmuclk_set_rate()
439 return -ENOENT; in rv1126_pmuclk_set_rate()
442 debug("%s %ld %ld\n", __func__, clk->id, rate); in rv1126_pmuclk_set_rate()
443 switch (clk->id) { in rv1126_pmuclk_set_rate()
452 ret = rv1126_i2c_set_pmuclk(priv, clk->id, rate); in rv1126_pmuclk_set_rate()
456 ret = rv1126_pwm_set_pmuclk(priv, clk->id, rate); in rv1126_pmuclk_set_rate()
465 return -ENOENT; in rv1126_pmuclk_set_rate()
471 static int rv1126_rtc32k_set_parent(struct clk *clk, struct clk *parent) in rv1126_rtc32k_set_parent() argument
473 struct rv1126_pmuclk_priv *priv = dev_get_priv(clk->dev); in rv1126_rtc32k_set_parent()
474 struct rv1126_pmucru *pmucru = priv->pmucru; in rv1126_rtc32k_set_parent()
476 if (parent->id == CLK_OSC0_DIV32K) in rv1126_rtc32k_set_parent()
477 rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK, in rv1126_rtc32k_set_parent()
480 rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK, in rv1126_rtc32k_set_parent()
486 static int rv1126_pmuclk_set_parent(struct clk *clk, struct clk *parent) in rv1126_pmuclk_set_parent() argument
488 switch (clk->id) { in rv1126_pmuclk_set_parent()
490 return rv1126_rtc32k_set_parent(clk, parent); in rv1126_pmuclk_set_parent()
492 return -ENOENT; in rv1126_pmuclk_set_parent()
505 priv->gpll_hz = rv1126_gpll_get_pmuclk(priv); in rv1126_pmuclk_probe()
514 priv->pmucru = dev_read_addr_ptr(dev); in rv1126_pmuclk_ofdata_to_platdata()
532 sf_priv->sf_reset_offset = offsetof(struct rv1126_pmucru, in rv1126_pmuclk_bind()
534 sf_priv->sf_reset_num = 2; in rv1126_pmuclk_bind()
535 sf_child->priv = sf_priv; in rv1126_pmuclk_bind()
542 { .compatible = "rockchip,rv1126-pmucru" },
560 struct rv1126_cru *cru = priv->cru; in rv1126_armclk_set_clk()
567 return -EINVAL; in rv1126_armclk_set_clk()
574 priv->cru, APLL); in rv1126_armclk_set_clk()
577 priv->cru, APLL, hz)) in rv1126_armclk_set_clk()
578 return -EINVAL; in rv1126_armclk_set_clk()
579 rk_clrsetreg(&cru->clksel_con[1], in rv1126_armclk_set_clk()
581 rate->pclk_div << CORE_DBG_DIV_SHIFT | in rv1126_armclk_set_clk()
582 rate->aclk_div << CORE_ACLK_DIV_SHIFT); in rv1126_armclk_set_clk()
584 rk_clrsetreg(&cru->clksel_con[1], in rv1126_armclk_set_clk()
586 rate->pclk_div << CORE_DBG_DIV_SHIFT | in rv1126_armclk_set_clk()
587 rate->aclk_div << CORE_ACLK_DIV_SHIFT); in rv1126_armclk_set_clk()
589 priv->cru, APLL, hz)) in rv1126_armclk_set_clk()
590 return -EINVAL; in rv1126_armclk_set_clk()
598 struct rv1126_cru *cru = priv->cru; in rv1126_pdcore_get_clk()
599 u32 con, div; in rv1126_pdcore_get_clk() local
601 con = readl(&cru->clksel_con[0]); in rv1126_pdcore_get_clk()
602 div = (con & CORE_HCLK_DIV_MASK) >> CORE_HCLK_DIV_SHIFT; in rv1126_pdcore_get_clk()
604 return DIV_TO_RATE(priv->gpll_hz, div); in rv1126_pdcore_get_clk()
609 struct rv1126_cru *cru = priv->cru; in rv1126_pdcore_set_clk()
611 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdcore_set_clk()
612 assert(src_clk_div - 1 <= 31); in rv1126_pdcore_set_clk()
614 rk_clrsetreg(&cru->clksel_con[0], CORE_HCLK_DIV_MASK, in rv1126_pdcore_set_clk()
615 (src_clk_div - 1) << CORE_HCLK_DIV_SHIFT); in rv1126_pdcore_set_clk()
622 struct rv1126_cru *cru = priv->cru; in rv1126_pdbus_get_clk()
623 u32 con, div, sel, parent; in rv1126_pdbus_get_clk() local
627 con = readl(&cru->clksel_con[2]); in rv1126_pdbus_get_clk()
628 div = (con & ACLK_PDBUS_DIV_MASK) >> ACLK_PDBUS_DIV_SHIFT; in rv1126_pdbus_get_clk()
631 parent = priv->gpll_hz; in rv1126_pdbus_get_clk()
633 parent = priv->cpll_hz; in rv1126_pdbus_get_clk()
635 return -ENOENT; in rv1126_pdbus_get_clk()
638 con = readl(&cru->clksel_con[2]); in rv1126_pdbus_get_clk()
639 div = (con & HCLK_PDBUS_DIV_MASK) >> HCLK_PDBUS_DIV_SHIFT; in rv1126_pdbus_get_clk()
642 parent = priv->gpll_hz; in rv1126_pdbus_get_clk()
644 parent = priv->cpll_hz; in rv1126_pdbus_get_clk()
646 return -ENOENT; in rv1126_pdbus_get_clk()
650 con = readl(&cru->clksel_con[3]); in rv1126_pdbus_get_clk()
651 div = (con & PCLK_PDBUS_DIV_MASK) >> PCLK_PDBUS_DIV_SHIFT; in rv1126_pdbus_get_clk()
654 parent = priv->gpll_hz; in rv1126_pdbus_get_clk()
656 parent = priv->cpll_hz; in rv1126_pdbus_get_clk()
658 return -ENOENT; in rv1126_pdbus_get_clk()
661 return -ENOENT; in rv1126_pdbus_get_clk()
664 return DIV_TO_RATE(parent, div); in rv1126_pdbus_get_clk()
670 struct rv1126_cru *cru = priv->cru; in rv1126_pdbus_set_clk()
676 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdbus_set_clk()
679 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rv1126_pdbus_set_clk()
682 assert(src_clk_div - 1 <= 31); in rv1126_pdbus_set_clk()
683 rk_clrsetreg(&cru->clksel_con[2], in rv1126_pdbus_set_clk()
686 (src_clk_div - 1) << ACLK_PDBUS_DIV_SHIFT); in rv1126_pdbus_set_clk()
689 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdbus_set_clk()
690 assert(src_clk_div - 1 <= 31); in rv1126_pdbus_set_clk()
691 rk_clrsetreg(&cru->clksel_con[2], in rv1126_pdbus_set_clk()
694 (src_clk_div - 1) << HCLK_PDBUS_DIV_SHIFT); in rv1126_pdbus_set_clk()
698 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdbus_set_clk()
699 assert(src_clk_div - 1 <= 31); in rv1126_pdbus_set_clk()
700 rk_clrsetreg(&cru->clksel_con[3], in rv1126_pdbus_set_clk()
703 (src_clk_div - 1) << PCLK_PDBUS_DIV_SHIFT); in rv1126_pdbus_set_clk()
708 return -EINVAL; in rv1126_pdbus_set_clk()
716 struct rv1126_cru *cru = priv->cru; in rv1126_pdphp_get_clk()
717 u32 con, div, parent; in rv1126_pdphp_get_clk() local
721 con = readl(&cru->clksel_con[53]); in rv1126_pdphp_get_clk()
722 div = (con & ACLK_PDPHP_DIV_MASK) >> ACLK_PDPHP_DIV_SHIFT; in rv1126_pdphp_get_clk()
723 parent = priv->gpll_hz; in rv1126_pdphp_get_clk()
726 con = readl(&cru->clksel_con[53]); in rv1126_pdphp_get_clk()
727 div = (con & HCLK_PDPHP_DIV_MASK) >> HCLK_PDPHP_DIV_SHIFT; in rv1126_pdphp_get_clk()
728 parent = priv->gpll_hz; in rv1126_pdphp_get_clk()
731 return -ENOENT; in rv1126_pdphp_get_clk()
734 return DIV_TO_RATE(parent, div); in rv1126_pdphp_get_clk()
740 struct rv1126_cru *cru = priv->cru; in rv1126_pdphp_set_clk()
743 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdphp_set_clk()
744 assert(src_clk_div - 1 <= 31); in rv1126_pdphp_set_clk()
748 rk_clrsetreg(&cru->clksel_con[53], in rv1126_pdphp_set_clk()
751 (src_clk_div - 1) << ACLK_PDPHP_DIV_SHIFT); in rv1126_pdphp_set_clk()
754 rk_clrsetreg(&cru->clksel_con[53], in rv1126_pdphp_set_clk()
756 (src_clk_div - 1) << HCLK_PDPHP_DIV_SHIFT); in rv1126_pdphp_set_clk()
760 return -EINVAL; in rv1126_pdphp_set_clk()
768 struct rv1126_cru *cru = priv->cru; in rv1126_pdaudio_get_clk()
769 u32 con, div; in rv1126_pdaudio_get_clk() local
771 con = readl(&cru->clksel_con[26]); in rv1126_pdaudio_get_clk()
772 div = (con & HCLK_PDAUDIO_DIV_MASK) >> HCLK_PDAUDIO_DIV_SHIFT; in rv1126_pdaudio_get_clk()
774 return DIV_TO_RATE(priv->gpll_hz, div); in rv1126_pdaudio_get_clk()
779 struct rv1126_cru *cru = priv->cru; in rv1126_pdaudio_set_clk()
782 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdaudio_set_clk()
783 assert(src_clk_div - 1 <= 31); in rv1126_pdaudio_set_clk()
785 rk_clrsetreg(&cru->clksel_con[26], HCLK_PDAUDIO_DIV_MASK, in rv1126_pdaudio_set_clk()
786 (src_clk_div - 1) << HCLK_PDAUDIO_DIV_SHIFT); in rv1126_pdaudio_set_clk()
793 struct rv1126_cru *cru = priv->cru; in rv1126_i2c_get_clk()
794 u32 div, con; in rv1126_i2c_get_clk() local
798 con = readl(&cru->clksel_con[5]); in rv1126_i2c_get_clk()
799 div = (con & CLK_I2C1_DIV_MASK) >> CLK_I2C1_DIV_SHIFT; in rv1126_i2c_get_clk()
802 con = readl(&cru->clksel_con[5]); in rv1126_i2c_get_clk()
803 div = (con & CLK_I2C3_DIV_MASK) >> CLK_I2C3_DIV_SHIFT; in rv1126_i2c_get_clk()
806 con = readl(&cru->clksel_con[6]); in rv1126_i2c_get_clk()
807 div = (con & CLK_I2C4_DIV_MASK) >> CLK_I2C4_DIV_SHIFT; in rv1126_i2c_get_clk()
810 con = readl(&cru->clksel_con[6]); in rv1126_i2c_get_clk()
811 div = (con & CLK_I2C5_DIV_MASK) >> CLK_I2C5_DIV_SHIFT; in rv1126_i2c_get_clk()
814 return -ENOENT; in rv1126_i2c_get_clk()
817 return DIV_TO_RATE(priv->gpll_hz, div); in rv1126_i2c_get_clk()
823 struct rv1126_cru *cru = priv->cru; in rv1126_i2c_set_clk()
826 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_i2c_set_clk()
827 assert(src_clk_div - 1 <= 127); in rv1126_i2c_set_clk()
831 rk_clrsetreg(&cru->clksel_con[5], CLK_I2C1_DIV_MASK, in rv1126_i2c_set_clk()
832 (src_clk_div - 1) << CLK_I2C1_DIV_SHIFT); in rv1126_i2c_set_clk()
835 rk_clrsetreg(&cru->clksel_con[5], CLK_I2C3_DIV_MASK, in rv1126_i2c_set_clk()
836 (src_clk_div - 1) << CLK_I2C3_DIV_SHIFT); in rv1126_i2c_set_clk()
839 rk_clrsetreg(&cru->clksel_con[6], CLK_I2C4_DIV_MASK, in rv1126_i2c_set_clk()
840 (src_clk_div - 1) << CLK_I2C4_DIV_SHIFT); in rv1126_i2c_set_clk()
843 rk_clrsetreg(&cru->clksel_con[6], CLK_I2C5_DIV_MASK, in rv1126_i2c_set_clk()
844 (src_clk_div - 1) << CLK_I2C5_DIV_SHIFT); in rv1126_i2c_set_clk()
847 return -ENOENT; in rv1126_i2c_set_clk()
855 struct rv1126_cru *cru = priv->cru; in rv1126_spi_get_clk()
856 u32 div, con; in rv1126_spi_get_clk() local
858 con = readl(&cru->clksel_con[8]); in rv1126_spi_get_clk()
859 div = (con & CLK_SPI1_DIV_MASK) >> CLK_SPI1_DIV_SHIFT; in rv1126_spi_get_clk()
861 return DIV_TO_RATE(priv->gpll_hz, div); in rv1126_spi_get_clk()
866 struct rv1126_cru *cru = priv->cru; in rv1126_spi_set_clk()
869 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_spi_set_clk()
870 assert(src_clk_div - 1 <= 127); in rv1126_spi_set_clk()
872 rk_clrsetreg(&cru->clksel_con[8], in rv1126_spi_set_clk()
875 (src_clk_div - 1) << CLK_SPI1_DIV_SHIFT); in rv1126_spi_set_clk()
882 struct rv1126_cru *cru = priv->cru; in rv1126_pwm_get_clk()
883 u32 div, sel, con; in rv1126_pwm_get_clk() local
885 con = readl(&cru->clksel_con[9]); in rv1126_pwm_get_clk()
887 div = (con & CLK_PWM2_DIV_MASK) >> CLK_PWM2_DIV_SHIFT; in rv1126_pwm_get_clk()
891 return DIV_TO_RATE(priv->gpll_hz, div); in rv1126_pwm_get_clk()
896 struct rv1126_cru *cru = priv->cru; in rv1126_pwm_set_clk()
900 rk_clrsetreg(&cru->clksel_con[9], CLK_PWM2_SEL_MASK, in rv1126_pwm_set_clk()
902 rk_clrsetreg(&cru->clksel_con[9], CLK_PWM2_DIV_MASK, 0); in rv1126_pwm_set_clk()
904 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pwm_set_clk()
905 assert(src_clk_div - 1 <= 127); in rv1126_pwm_set_clk()
906 rk_clrsetreg(&cru->clksel_con[9], CLK_PWM2_DIV_MASK, in rv1126_pwm_set_clk()
907 (src_clk_div - 1) << CLK_PWM2_DIV_SHIFT); in rv1126_pwm_set_clk()
908 rk_clrsetreg(&cru->clksel_con[9], CLK_PWM2_SEL_MASK, in rv1126_pwm_set_clk()
917 struct rv1126_cru *cru = priv->cru; in rv1126_saradc_get_clk()
918 u32 div, con; in rv1126_saradc_get_clk() local
920 con = readl(&cru->clksel_con[20]); in rv1126_saradc_get_clk()
921 div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT; in rv1126_saradc_get_clk()
923 return DIV_TO_RATE(OSC_HZ, div); in rv1126_saradc_get_clk()
928 struct rv1126_cru *cru = priv->cru; in rv1126_saradc_set_clk()
932 assert(src_clk_div - 1 <= 2047); in rv1126_saradc_set_clk()
933 rk_clrsetreg(&cru->clksel_con[20], CLK_SARADC_DIV_MASK, in rv1126_saradc_set_clk()
934 (src_clk_div - 1) << CLK_SARADC_DIV_SHIFT); in rv1126_saradc_set_clk()
941 struct rv1126_cru *cru = priv->cru; in rv1126_crypto_get_clk()
942 u32 div, sel, con, parent; in rv1126_crypto_get_clk() local
946 con = readl(&cru->clksel_con[7]); in rv1126_crypto_get_clk()
947 div = (con & CLK_CRYPTO_CORE_DIV_MASK) >> CLK_CRYPTO_CORE_DIV_SHIFT; in rv1126_crypto_get_clk()
950 parent = priv->gpll_hz; in rv1126_crypto_get_clk()
952 parent = priv->cpll_hz; in rv1126_crypto_get_clk()
954 return -ENOENT; in rv1126_crypto_get_clk()
957 con = readl(&cru->clksel_con[7]); in rv1126_crypto_get_clk()
958 div = (con & CLK_CRYPTO_PKA_DIV_MASK) >> CLK_CRYPTO_PKA_DIV_SHIFT; in rv1126_crypto_get_clk()
961 parent = priv->gpll_hz; in rv1126_crypto_get_clk()
963 parent = priv->cpll_hz; in rv1126_crypto_get_clk()
965 return -ENOENT; in rv1126_crypto_get_clk()
968 con = readl(&cru->clksel_con[4]); in rv1126_crypto_get_clk()
969 div = (con & ACLK_CRYPTO_DIV_MASK) >> ACLK_CRYPTO_DIV_SHIFT; in rv1126_crypto_get_clk()
972 parent = priv->gpll_hz; in rv1126_crypto_get_clk()
974 parent = priv->cpll_hz; in rv1126_crypto_get_clk()
976 return -ENOENT; in rv1126_crypto_get_clk()
979 return -ENOENT; in rv1126_crypto_get_clk()
982 return DIV_TO_RATE(parent, div); in rv1126_crypto_get_clk()
988 struct rv1126_cru *cru = priv->cru; in rv1126_crypto_set_clk()
991 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_crypto_set_clk()
992 assert(src_clk_div - 1 <= 31); in rv1126_crypto_set_clk()
996 rk_clrsetreg(&cru->clksel_con[7], in rv1126_crypto_set_clk()
1001 (src_clk_div - 1) << CLK_CRYPTO_CORE_DIV_SHIFT); in rv1126_crypto_set_clk()
1004 rk_clrsetreg(&cru->clksel_con[7], in rv1126_crypto_set_clk()
1009 (src_clk_div - 1) << CLK_CRYPTO_PKA_DIV_SHIFT); in rv1126_crypto_set_clk()
1012 rk_clrsetreg(&cru->clksel_con[4], in rv1126_crypto_set_clk()
1015 (src_clk_div - 1) << ACLK_CRYPTO_DIV_SHIFT); in rv1126_crypto_set_clk()
1018 return -ENOENT; in rv1126_crypto_set_clk()
1026 struct rv1126_cru *cru = priv->cru; in rv1126_mmc_get_clk()
1027 u32 div, sel, con, con_id; in rv1126_mmc_get_clk() local
1044 return -ENOENT; in rv1126_mmc_get_clk()
1047 con = readl(&cru->clksel_con[con_id]); in rv1126_mmc_get_clk()
1048 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; in rv1126_mmc_get_clk()
1051 return DIV_TO_RATE(priv->gpll_hz, div) / 2; in rv1126_mmc_get_clk()
1053 return DIV_TO_RATE(priv->cpll_hz, div) / 2; in rv1126_mmc_get_clk()
1055 return DIV_TO_RATE(OSC_HZ, div) / 2; in rv1126_mmc_get_clk()
1057 return -ENOENT; in rv1126_mmc_get_clk()
1063 struct rv1126_cru *cru = priv->cru; in rv1126_mmc_set_clk()
1081 return -ENOENT; in rv1126_mmc_set_clk()
1085 /* mmc clock defaulg div 2 internal, need provide double in cru */ in rv1126_mmc_set_clk()
1086 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, rate); in rv1126_mmc_set_clk()
1091 rk_clrsetreg(&cru->clksel_con[con_id], in rv1126_mmc_set_clk()
1094 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rv1126_mmc_set_clk()
1096 rk_clrsetreg(&cru->clksel_con[con_id], in rv1126_mmc_set_clk()
1099 (src_clk_div - 1) << EMMC_DIV_SHIFT); in rv1126_mmc_set_clk()
1107 struct rv1126_cru *cru = priv->cru; in rv1126_sfc_get_clk()
1108 u32 div, sel, con, parent; in rv1126_sfc_get_clk() local
1110 con = readl(&cru->clksel_con[58]); in rv1126_sfc_get_clk()
1111 div = (con & SCLK_SFC_DIV_MASK) >> SCLK_SFC_DIV_SHIFT; in rv1126_sfc_get_clk()
1114 parent = priv->gpll_hz; in rv1126_sfc_get_clk()
1116 parent = priv->cpll_hz; in rv1126_sfc_get_clk()
1118 return -ENOENT; in rv1126_sfc_get_clk()
1120 return DIV_TO_RATE(parent, div); in rv1126_sfc_get_clk()
1125 struct rv1126_cru *cru = priv->cru; in rv1126_sfc_set_clk()
1128 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_sfc_set_clk()
1129 rk_clrsetreg(&cru->clksel_con[58], in rv1126_sfc_set_clk()
1132 (src_clk_div - 1) << SCLK_SFC_DIV_SHIFT); in rv1126_sfc_set_clk()
1139 struct rv1126_cru *cru = priv->cru; in rv1126_nand_get_clk()
1140 u32 div, sel, con, parent; in rv1126_nand_get_clk() local
1142 con = readl(&cru->clksel_con[59]); in rv1126_nand_get_clk()
1143 div = (con & CLK_NANDC_DIV_MASK) >> CLK_NANDC_DIV_SHIFT; in rv1126_nand_get_clk()
1146 parent = priv->gpll_hz; in rv1126_nand_get_clk()
1148 parent = priv->cpll_hz; in rv1126_nand_get_clk()
1150 return -ENOENT; in rv1126_nand_get_clk()
1152 return DIV_TO_RATE(parent, div); in rv1126_nand_get_clk()
1157 struct rv1126_cru *cru = priv->cru; in rv1126_nand_set_clk()
1160 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_nand_set_clk()
1161 rk_clrsetreg(&cru->clksel_con[59], in rv1126_nand_set_clk()
1164 (src_clk_div - 1) << CLK_NANDC_DIV_SHIFT); in rv1126_nand_set_clk()
1171 struct rv1126_cru *cru = priv->cru; in rv1126_aclk_vop_get_clk()
1172 u32 div, sel, con, parent; in rv1126_aclk_vop_get_clk() local
1174 con = readl(&cru->clksel_con[45]); in rv1126_aclk_vop_get_clk()
1175 div = (con & ACLK_PDVO_DIV_MASK) >> ACLK_PDVO_DIV_SHIFT; in rv1126_aclk_vop_get_clk()
1178 parent = priv->gpll_hz; in rv1126_aclk_vop_get_clk()
1180 parent = priv->cpll_hz; in rv1126_aclk_vop_get_clk()
1182 return -ENOENT; in rv1126_aclk_vop_get_clk()
1184 return DIV_TO_RATE(parent, div); in rv1126_aclk_vop_get_clk()
1189 struct rv1126_cru *cru = priv->cru; in rv1126_aclk_vop_set_clk()
1192 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_aclk_vop_set_clk()
1193 assert(src_clk_div - 1 <= 31); in rv1126_aclk_vop_set_clk()
1194 rk_clrsetreg(&cru->clksel_con[45], in rv1126_aclk_vop_set_clk()
1197 (src_clk_div - 1) << ACLK_PDVO_DIV_SHIFT); in rv1126_aclk_vop_set_clk()
1204 struct rv1126_cru *cru = priv->cru; in rv1126_dclk_vop_get_clk()
1205 u32 div, sel, con, parent; in rv1126_dclk_vop_get_clk() local
1207 con = readl(&cru->clksel_con[47]); in rv1126_dclk_vop_get_clk()
1208 div = (con & DCLK_VOP_DIV_MASK) >> DCLK_VOP_DIV_SHIFT; in rv1126_dclk_vop_get_clk()
1211 parent = priv->gpll_hz; in rv1126_dclk_vop_get_clk()
1213 parent = priv->cpll_hz; in rv1126_dclk_vop_get_clk()
1215 return -ENOENT; in rv1126_dclk_vop_get_clk()
1217 return DIV_TO_RATE(parent, div); in rv1126_dclk_vop_get_clk()
1222 struct rv1126_cru *cru = priv->cru; in rv1126_dclk_vop_set_clk()
1224 u32 i, div, best_div = 0, best_sel = 0; in rv1126_dclk_vop_set_clk() local
1229 pll_rate = priv->gpll_hz; in rv1126_dclk_vop_set_clk()
1232 pll_rate = priv->cpll_hz; in rv1126_dclk_vop_set_clk()
1236 return -EINVAL; in rv1126_dclk_vop_set_clk()
1239 div = DIV_ROUND_UP(pll_rate, rate); in rv1126_dclk_vop_set_clk()
1240 if (div > 255) in rv1126_dclk_vop_set_clk()
1242 now = pll_rate / div; in rv1126_dclk_vop_set_clk()
1243 if (abs(rate - now) < abs(rate - best_rate)) { in rv1126_dclk_vop_set_clk()
1245 best_div = div; in rv1126_dclk_vop_set_clk()
1253 rk_clrsetreg(&cru->clksel_con[47], in rv1126_dclk_vop_set_clk()
1256 (best_div - 1) << DCLK_VOP_DIV_SHIFT); in rv1126_dclk_vop_set_clk()
1259 return -EINVAL; in rv1126_dclk_vop_set_clk()
1268 struct rv1126_cru *cru = priv->cru; in rv1126_scr1_get_clk()
1269 u32 div, sel, con, parent; in rv1126_scr1_get_clk() local
1271 con = readl(&cru->clksel_con[3]); in rv1126_scr1_get_clk()
1272 div = (con & CLK_SCR1_DIV_MASK) >> CLK_SCR1_DIV_SHIFT; in rv1126_scr1_get_clk()
1275 parent = priv->gpll_hz; in rv1126_scr1_get_clk()
1277 parent = priv->cpll_hz; in rv1126_scr1_get_clk()
1279 return -ENOENT; in rv1126_scr1_get_clk()
1281 return DIV_TO_RATE(parent, div); in rv1126_scr1_get_clk()
1286 struct rv1126_cru *cru = priv->cru; in rv1126_scr1_set_clk()
1289 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_scr1_set_clk()
1290 assert(src_clk_div - 1 <= 31); in rv1126_scr1_set_clk()
1291 rk_clrsetreg(&cru->clksel_con[3], in rv1126_scr1_set_clk()
1294 (src_clk_div - 1) << CLK_SCR1_DIV_SHIFT); in rv1126_scr1_set_clk()
1301 struct rv1126_cru *cru = priv->cru; in rv1126_gmac_src_get_clk()
1302 u32 div, sel, con, parent; in rv1126_gmac_src_get_clk() local
1304 con = readl(&cru->clksel_con[63]); in rv1126_gmac_src_get_clk()
1305 div = (con & CLK_GMAC_SRC_DIV_MASK) >> CLK_GMAC_SRC_DIV_SHIFT; in rv1126_gmac_src_get_clk()
1308 parent = priv->cpll_hz; in rv1126_gmac_src_get_clk()
1310 parent = priv->gpll_hz; in rv1126_gmac_src_get_clk()
1312 return -ENOENT; in rv1126_gmac_src_get_clk()
1314 return DIV_TO_RATE(parent, div); in rv1126_gmac_src_get_clk()
1319 struct rv1126_cru *cru = priv->cru; in rv1126_gmac_src_set_clk()
1322 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rv1126_gmac_src_set_clk()
1323 assert(src_clk_div - 1 <= 31); in rv1126_gmac_src_set_clk()
1324 rk_clrsetreg(&cru->clksel_con[63], in rv1126_gmac_src_set_clk()
1327 (src_clk_div - 1) << CLK_GMAC_SRC_DIV_SHIFT); in rv1126_gmac_src_set_clk()
1334 struct rv1126_cru *cru = priv->cru; in rv1126_gmac_out_get_clk()
1335 u32 div, sel, con, parent; in rv1126_gmac_out_get_clk() local
1337 con = readl(&cru->clksel_con[61]); in rv1126_gmac_out_get_clk()
1338 div = (con & CLK_GMAC_OUT_DIV_MASK) >> CLK_GMAC_OUT_DIV_SHIFT; in rv1126_gmac_out_get_clk()
1341 parent = priv->cpll_hz; in rv1126_gmac_out_get_clk()
1343 parent = priv->gpll_hz; in rv1126_gmac_out_get_clk()
1345 return -ENOENT; in rv1126_gmac_out_get_clk()
1347 return DIV_TO_RATE(parent, div); in rv1126_gmac_out_get_clk()
1352 struct rv1126_cru *cru = priv->cru; in rv1126_gmac_out_set_clk()
1355 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rv1126_gmac_out_set_clk()
1356 assert(src_clk_div - 1 <= 31); in rv1126_gmac_out_set_clk()
1357 rk_clrsetreg(&cru->clksel_con[61], in rv1126_gmac_out_set_clk()
1360 (src_clk_div - 1) << CLK_GMAC_OUT_DIV_SHIFT); in rv1126_gmac_out_set_clk()
1367 struct rv1126_cru *cru = priv->cru; in rv1126_gmac_tx_rx_set_clk()
1370 con = readl(&cru->gmac_con); in rv1126_gmac_tx_rx_set_clk()
1380 rk_clrsetreg(&cru->gmac_con, RGMII_CLK_SEL_MASK, in rv1126_gmac_tx_rx_set_clk()
1387 rk_clrsetreg(&cru->gmac_con, RMII_CLK_SEL_MASK, in rv1126_gmac_tx_rx_set_clk()
1396 struct rv1126_cru *cru = priv->cru; in rv1126_pclk_gmac_get_clk()
1397 u32 div, con, parent; in rv1126_pclk_gmac_get_clk() local
1401 con = readl(&cru->clksel_con[63]); in rv1126_pclk_gmac_get_clk()
1402 div = (con & PCLK_GMAC_DIV_MASK) >> PCLK_GMAC_DIV_SHIFT; in rv1126_pclk_gmac_get_clk()
1404 return DIV_TO_RATE(parent, div); in rv1126_pclk_gmac_get_clk()
1410 struct rv1126_cru *cru = priv->cru; in rv1126_clk_mipicsi_out_get_clk()
1411 u32 div, fracdiv, sel, con, n, m, parent = priv->gpll_hz; in rv1126_clk_mipicsi_out_get_clk() local
1413 con = readl(&cru->clksel_con[73]); in rv1126_clk_mipicsi_out_get_clk()
1414 div = (con & MIPICSI_OUT_DIV_MASK) >> MIPICSI_OUT_DIV_SHIFT; in rv1126_clk_mipicsi_out_get_clk()
1419 parent = DIV_TO_RATE(parent, div); in rv1126_clk_mipicsi_out_get_clk()
1420 fracdiv = readl(&cru->clksel_con[74]); in rv1126_clk_mipicsi_out_get_clk()
1426 return DIV_TO_RATE(parent, div); in rv1126_clk_mipicsi_out_get_clk()
1431 { struct rv1126_cru *cru = priv->cru; in rv1126_clk_mipicsi_out_set_clk()
1435 rk_clrsetreg(&cru->clksel_con[73], MIPICSI_OUT_SEL_MASK, in rv1126_clk_mipicsi_out_set_clk()
1438 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, 297000000); in rv1126_clk_mipicsi_out_set_clk()
1439 rk_clrsetreg(&cru->clksel_con[73], MIPICSI_OUT_DIV_MASK, in rv1126_clk_mipicsi_out_set_clk()
1440 (src_clk_div - 1) << MIPICSI_OUT_DIV_SHIFT); in rv1126_clk_mipicsi_out_set_clk()
1441 rk_clrsetreg(&cru->clksel_con[73], MIPICSI_OUT_SEL_MASK, in rv1126_clk_mipicsi_out_set_clk()
1443 writel(4 << 16 | 44, &cru->clksel_con[74]); in rv1126_clk_mipicsi_out_set_clk()
1445 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_clk_mipicsi_out_set_clk()
1446 assert(src_clk_div - 1 <= 31); in rv1126_clk_mipicsi_out_set_clk()
1447 rk_clrsetreg(&cru->clksel_con[73], MIPICSI_OUT_DIV_MASK, in rv1126_clk_mipicsi_out_set_clk()
1448 (src_clk_div - 1) << MIPICSI_OUT_DIV_SHIFT); in rv1126_clk_mipicsi_out_set_clk()
1449 rk_clrsetreg(&cru->clksel_con[73], MIPICSI_OUT_SEL_MASK, in rv1126_clk_mipicsi_out_set_clk()
1459 struct rv1126_cru *cru = priv->cru; in rv1126_clk_pdvi_ispp_get_clk()
1460 u32 div, sel, con, parent, con_id; in rv1126_clk_pdvi_ispp_get_clk() local
1473 return -ENOENT; in rv1126_clk_pdvi_ispp_get_clk()
1476 con = readl(&cru->clksel_con[con_id]); in rv1126_clk_pdvi_ispp_get_clk()
1477 div = (con & ACLK_PDVI_DIV_MASK) >> ACLK_PDVI_DIV_SHIFT; in rv1126_clk_pdvi_ispp_get_clk()
1480 parent = priv->gpll_hz; in rv1126_clk_pdvi_ispp_get_clk()
1482 parent = priv->cpll_hz; in rv1126_clk_pdvi_ispp_get_clk()
1484 parent = priv->hpll_hz; in rv1126_clk_pdvi_ispp_get_clk()
1486 return -ENOENT; in rv1126_clk_pdvi_ispp_get_clk()
1488 return DIV_TO_RATE(parent, div); in rv1126_clk_pdvi_ispp_get_clk()
1494 struct rv1126_cru *cru = priv->cru; in rv1126_clk_pdvi_ispp_set_clk()
1508 return -ENOENT; in rv1126_clk_pdvi_ispp_set_clk()
1511 if (!(priv->cpll_hz % rate)) { in rv1126_clk_pdvi_ispp_set_clk()
1512 parent = priv->cpll_hz; in rv1126_clk_pdvi_ispp_set_clk()
1514 } else if (!(priv->hpll_hz % rate)) { in rv1126_clk_pdvi_ispp_set_clk()
1515 parent = priv->hpll_hz; in rv1126_clk_pdvi_ispp_set_clk()
1518 parent = priv->gpll_hz; in rv1126_clk_pdvi_ispp_set_clk()
1523 assert(src_clk_div - 1 <= 31); in rv1126_clk_pdvi_ispp_set_clk()
1524 rk_clrsetreg(&cru->clksel_con[con_id], in rv1126_clk_pdvi_ispp_set_clk()
1527 (src_clk_div - 1) << ACLK_PDVI_DIV_SHIFT); in rv1126_clk_pdvi_ispp_set_clk()
1534 struct rv1126_cru *cru = priv->cru; in rv1126_clk_isp_get_clk()
1535 u32 div, sel, con, parent; in rv1126_clk_isp_get_clk() local
1537 con = readl(&cru->clksel_con[50]); in rv1126_clk_isp_get_clk()
1538 div = (con & CLK_ISP_DIV_MASK) >> CLK_ISP_DIV_SHIFT; in rv1126_clk_isp_get_clk()
1541 parent = priv->gpll_hz; in rv1126_clk_isp_get_clk()
1543 parent = priv->cpll_hz; in rv1126_clk_isp_get_clk()
1545 parent = priv->hpll_hz; in rv1126_clk_isp_get_clk()
1547 return -ENOENT; in rv1126_clk_isp_get_clk()
1549 return DIV_TO_RATE(parent, div); in rv1126_clk_isp_get_clk()
1554 struct rv1126_cru *cru = priv->cru; in rv1126_clk_isp_set_clk()
1557 if (!(priv->cpll_hz % rate)) { in rv1126_clk_isp_set_clk()
1558 parent = priv->cpll_hz; in rv1126_clk_isp_set_clk()
1560 } else if (!(priv->hpll_hz % rate)) { in rv1126_clk_isp_set_clk()
1561 parent = priv->hpll_hz; in rv1126_clk_isp_set_clk()
1564 parent = priv->gpll_hz; in rv1126_clk_isp_set_clk()
1569 assert(src_clk_div - 1 <= 31); in rv1126_clk_isp_set_clk()
1570 rk_clrsetreg(&cru->clksel_con[50], in rv1126_clk_isp_set_clk()
1573 (src_clk_div - 1) << CLK_ISP_DIV_SHIFT); in rv1126_clk_isp_set_clk()
1581 struct rv1126_cru *cru = priv->cru; in rv1126_dclk_decom_get_clk()
1582 u32 div, sel, con, parent; in rv1126_dclk_decom_get_clk() local
1584 con = readl(&cru->clksel_con[25]); in rv1126_dclk_decom_get_clk()
1585 div = (con & DCLK_DECOM_DIV_MASK) >> DCLK_DECOM_DIV_SHIFT; in rv1126_dclk_decom_get_clk()
1588 parent = priv->gpll_hz; in rv1126_dclk_decom_get_clk()
1590 parent = priv->cpll_hz; in rv1126_dclk_decom_get_clk()
1592 return -ENOENT; in rv1126_dclk_decom_get_clk()
1594 return DIV_TO_RATE(parent, div); in rv1126_dclk_decom_get_clk()
1599 struct rv1126_cru *cru = priv->cru; in rv1126_dclk_decom_set_clk()
1602 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_dclk_decom_set_clk()
1603 assert(src_clk_div - 1 <= 127); in rv1126_dclk_decom_set_clk()
1604 rk_clrsetreg(&cru->clksel_con[25], in rv1126_dclk_decom_set_clk()
1607 (src_clk_div - 1) << DCLK_DECOM_DIV_SHIFT); in rv1126_dclk_decom_set_clk()
1612 static ulong rv1126_clk_get_rate(struct clk *clk) in rv1126_clk_get_rate() argument
1614 struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); in rv1126_clk_get_rate()
1617 if (!priv->gpll_hz) { in rv1126_clk_get_rate()
1618 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); in rv1126_clk_get_rate()
1619 return -ENOENT; in rv1126_clk_get_rate()
1622 switch (clk->id) { in rv1126_clk_get_rate()
1625 rate = rockchip_pll_get_rate(&rv1126_pll_clks[APLL], priv->cru, in rv1126_clk_get_rate()
1629 rate = rockchip_pll_get_rate(&rv1126_pll_clks[CPLL], priv->cru, in rv1126_clk_get_rate()
1633 rate = rockchip_pll_get_rate(&rv1126_pll_clks[HPLL], priv->cru, in rv1126_clk_get_rate()
1637 rate = rockchip_pll_get_rate(&rv1126_pll_clks[DPLL], priv->cru, in rv1126_clk_get_rate()
1647 rate = rv1126_pdbus_get_clk(priv, clk->id); in rv1126_clk_get_rate()
1651 rate = rv1126_pdphp_get_clk(priv, clk->id); in rv1126_clk_get_rate()
1660 rate = rv1126_i2c_get_clk(priv, clk->id); in rv1126_clk_get_rate()
1674 rate = rv1126_crypto_get_clk(priv, clk->id); in rv1126_clk_get_rate()
1683 rate = rv1126_mmc_get_clk(priv, clk->id); in rv1126_clk_get_rate()
1720 rate = rv1126_clk_pdvi_ispp_get_clk(priv, clk->id); in rv1126_clk_get_rate()
1727 return -ENOENT; in rv1126_clk_get_rate()
1733 static ulong rv1126_clk_set_rate(struct clk *clk, ulong rate) in rv1126_clk_set_rate() argument
1735 struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); in rv1126_clk_set_rate()
1738 if (!priv->gpll_hz) { in rv1126_clk_set_rate()
1739 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); in rv1126_clk_set_rate()
1740 return -ENOENT; in rv1126_clk_set_rate()
1743 switch (clk->id) { in rv1126_clk_set_rate()
1746 if (priv->armclk_hz) in rv1126_clk_set_rate()
1748 priv->armclk_hz = rate; in rv1126_clk_set_rate()
1751 ret = rockchip_pll_set_rate(&rv1126_pll_clks[CPLL], priv->cru, in rv1126_clk_set_rate()
1755 ret = rockchip_pll_set_rate(&rv1126_pll_clks[HPLL], priv->cru, in rv1126_clk_set_rate()
1762 ret = rv1126_pdbus_set_clk(priv, clk->id, rate); in rv1126_clk_set_rate()
1766 ret = rv1126_pdphp_set_clk(priv, clk->id, rate); in rv1126_clk_set_rate()
1778 ret = rv1126_i2c_set_clk(priv, clk->id, rate); in rv1126_clk_set_rate()
1792 ret = rv1126_crypto_set_clk(priv, clk->id, rate); in rv1126_clk_set_rate()
1800 ret = rv1126_mmc_set_clk(priv, clk->id, rate); in rv1126_clk_set_rate()
1837 ret = rv1126_clk_pdvi_ispp_set_clk(priv, clk->id, rate); in rv1126_clk_set_rate()
1844 return -ENOENT; in rv1126_clk_set_rate()
1857 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
1862 int rv1126_mmc_get_phase(struct clk *clk) in rv1126_mmc_get_phase() argument
1864 struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); in rv1126_mmc_get_phase()
1865 struct rv1126_cru *cru = priv->cru; in rv1126_mmc_get_phase()
1870 rate = rv1126_clk_get_rate(clk); in rv1126_mmc_get_phase()
1874 if (clk->id == SCLK_EMMC_SAMPLE) in rv1126_mmc_get_phase()
1875 raw_value = readl(&cru->emmc_con[1]); in rv1126_mmc_get_phase()
1876 else if (clk->id == SCLK_SDMMC_SAMPLE) in rv1126_mmc_get_phase()
1877 raw_value = readl(&cru->sdmmc_con[1]); in rv1126_mmc_get_phase()
1879 raw_value = readl(&cru->sdio_con[1]); in rv1126_mmc_get_phase()
1897 int rv1126_mmc_set_phase(struct clk *clk, u32 degrees) in rv1126_mmc_set_phase() argument
1899 struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); in rv1126_mmc_set_phase()
1900 struct rv1126_cru *cru = priv->cru; in rv1126_mmc_set_phase()
1905 rate = rv1126_clk_get_rate(clk); in rv1126_mmc_set_phase()
1914 * don't overflow 32-bit / 64-bit numbers. in rv1126_mmc_set_phase()
1928 if (clk->id == SCLK_EMMC_SAMPLE) in rv1126_mmc_set_phase()
1929 writel(raw_value | 0xffff0000, &cru->emmc_con[1]); in rv1126_mmc_set_phase()
1930 else if (clk->id == SCLK_SDMMC_SAMPLE) in rv1126_mmc_set_phase()
1931 writel(raw_value | 0xffff0000, &cru->sdmmc_con[1]); in rv1126_mmc_set_phase()
1933 writel(raw_value | 0xffff0000, &cru->sdio_con[1]); in rv1126_mmc_set_phase()
1936 degrees, delay_num, raw_value, rv1126_mmc_get_phase(clk)); in rv1126_mmc_set_phase()
1941 static int rv1126_clk_get_phase(struct clk *clk) in rv1126_clk_get_phase() argument
1945 debug("%s %ld\n", __func__, clk->id); in rv1126_clk_get_phase()
1946 switch (clk->id) { in rv1126_clk_get_phase()
1950 ret = rv1126_mmc_get_phase(clk); in rv1126_clk_get_phase()
1953 return -ENOENT; in rv1126_clk_get_phase()
1959 static int rv1126_clk_set_phase(struct clk *clk, int degrees) in rv1126_clk_set_phase() argument
1963 debug("%s %ld\n", __func__, clk->id); in rv1126_clk_set_phase()
1964 switch (clk->id) { in rv1126_clk_set_phase()
1968 ret = rv1126_mmc_set_phase(clk, degrees); in rv1126_clk_set_phase()
1971 return -ENOENT; in rv1126_clk_set_phase()
1978 static int rv1126_gmac_src_set_parent(struct clk *clk, struct clk *parent) in rv1126_gmac_src_set_parent() argument
1980 struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); in rv1126_gmac_src_set_parent()
1981 struct rv1126_grf *grf = priv->grf; in rv1126_gmac_src_set_parent()
1983 if (parent->id == CLK_GMAC_SRC_M0) in rv1126_gmac_src_set_parent()
1984 rk_clrsetreg(&grf->iofunc_con1, GMAC_SRC_SEL_MASK, in rv1126_gmac_src_set_parent()
1986 else if(parent->id == CLK_GMAC_SRC_M1) in rv1126_gmac_src_set_parent()
1987 rk_clrsetreg(&grf->iofunc_con1, GMAC_SRC_SEL_MASK, in rv1126_gmac_src_set_parent()
1993 static int rv1126_gmac_src_m0_set_parent(struct clk *clk, struct clk *parent) in rv1126_gmac_src_m0_set_parent() argument
1995 struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); in rv1126_gmac_src_m0_set_parent()
1996 struct rv1126_cru *cru = priv->cru; in rv1126_gmac_src_m0_set_parent()
1998 if (parent->id == CLK_GMAC_DIV) in rv1126_gmac_src_m0_set_parent()
1999 rk_clrsetreg(&cru->gmac_con, GMAC_SRC_M0_SEL_MASK, in rv1126_gmac_src_m0_set_parent()
2002 rk_clrsetreg(&cru->gmac_con, GMAC_SRC_M0_SEL_MASK, in rv1126_gmac_src_m0_set_parent()
2008 static int rv1126_gmac_src_m1_set_parent(struct clk *clk, struct clk *parent) in rv1126_gmac_src_m1_set_parent() argument
2010 struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); in rv1126_gmac_src_m1_set_parent()
2011 struct rv1126_cru *cru = priv->cru; in rv1126_gmac_src_m1_set_parent()
2013 if (parent->id == CLK_GMAC_DIV) in rv1126_gmac_src_m1_set_parent()
2014 rk_clrsetreg(&cru->gmac_con, GMAC_SRC_M1_SEL_MASK, in rv1126_gmac_src_m1_set_parent()
2017 rk_clrsetreg(&cru->gmac_con, GMAC_SRC_M1_SEL_MASK, in rv1126_gmac_src_m1_set_parent()
2023 static int rv1126_gmac_tx_rx_set_parent(struct clk *clk, struct clk *parent) in rv1126_gmac_tx_rx_set_parent() argument
2025 struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); in rv1126_gmac_tx_rx_set_parent()
2026 struct rv1126_cru *cru = priv->cru; in rv1126_gmac_tx_rx_set_parent()
2028 if (parent->id == RGMII_MODE_CLK) in rv1126_gmac_tx_rx_set_parent()
2029 rk_clrsetreg(&cru->gmac_con, GMAC_MODE_SEL_MASK, in rv1126_gmac_tx_rx_set_parent()
2032 rk_clrsetreg(&cru->gmac_con, GMAC_MODE_SEL_MASK, in rv1126_gmac_tx_rx_set_parent()
2038 static int rv1126_clk_set_parent(struct clk *clk, struct clk *parent) in rv1126_clk_set_parent() argument
2040 switch (clk->id) { in rv1126_clk_set_parent()
2042 return rv1126_gmac_src_set_parent(clk, parent); in rv1126_clk_set_parent()
2044 return rv1126_gmac_src_m0_set_parent(clk, parent); in rv1126_clk_set_parent()
2046 return rv1126_gmac_src_m1_set_parent(clk, parent); in rv1126_clk_set_parent()
2048 return rv1126_gmac_tx_rx_set_parent(clk, parent); in rv1126_clk_set_parent()
2050 return -ENOENT; in rv1126_clk_set_parent()
2074 if (priv->gpll_hz != OSC_HZ) { in rv1126_gpll_set_rate()
2084 * the child div is big enough for gpll 1188MHz, in rv1126_gpll_set_rate()
2088 pmu_priv->pmucru, GPLL, rate)) in rv1126_gpll_set_rate()
2089 return -EINVAL; in rv1126_gpll_set_rate()
2090 pmu_priv->gpll_hz = rate; in rv1126_gpll_set_rate()
2091 priv->gpll_hz = rate; in rv1126_gpll_set_rate()
2116 priv->gpll_hz = pmu_priv->gpll_hz; in rv1126_gpll_set_clk()
2120 return -EINVAL; in rv1126_gpll_set_clk()
2133 priv->sync_kernel = false; in rv1126_clk_init()
2134 if (!priv->armclk_enter_hz) { in rv1126_clk_init()
2135 priv->armclk_enter_hz = in rv1126_clk_init()
2137 priv->cru, APLL); in rv1126_clk_init()
2138 priv->armclk_init_hz = priv->armclk_enter_hz ; in rv1126_clk_init()
2141 if (priv->armclk_init_hz != APLL_HZ) { in rv1126_clk_init()
2144 priv->armclk_init_hz = APLL_HZ; in rv1126_clk_init()
2146 if (priv->cpll_hz != CPLL_HZ) { in rv1126_clk_init()
2147 ret = rockchip_pll_set_rate(&rv1126_pll_clks[CPLL], priv->cru, in rv1126_clk_init()
2150 priv->cpll_hz = CPLL_HZ; in rv1126_clk_init()
2152 if (priv->hpll_hz != HPLL_HZ) { in rv1126_clk_init()
2153 ret = rockchip_pll_set_rate(&rv1126_pll_clks[HPLL], priv->cru, in rv1126_clk_init()
2156 priv->hpll_hz = HPLL_HZ; in rv1126_clk_init()
2158 if (priv->gpll_hz != GPLL_HZ) in rv1126_clk_init()
2183 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rv1126_clk_probe()
2184 if (IS_ERR(priv->grf)) in rv1126_clk_probe()
2185 return PTR_ERR(priv->grf); in rv1126_clk_probe()
2189 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ in rv1126_clk_probe()
2194 priv->sync_kernel = true; in rv1126_clk_probe()
2203 priv->cru = dev_read_addr_ptr(dev); in rv1126_clk_ofdata_to_platdata()
2222 priv->glb_srst_fst_value = offsetof(struct rv1126_cru, in rv1126_clk_bind()
2224 priv->glb_srst_snd_value = offsetof(struct rv1126_cru, in rv1126_clk_bind()
2226 sys_child->priv = priv; in rv1126_clk_bind()
2235 sf_priv->sf_reset_offset = offsetof(struct rv1126_cru, in rv1126_clk_bind()
2237 sf_priv->sf_reset_num = 15; in rv1126_clk_bind()
2238 sf_child->priv = sf_priv; in rv1126_clk_bind()
2245 { .compatible = "rockchip,rv1126-cru" },
2262 * soc_clk_dump() - Print clock frequencies
2265 * Implementation for the clk dump command.
2272 struct clk clk; in soc_clk_dump() local
2294 printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", in soc_clk_dump()
2295 priv->sync_kernel ? "sync kernel" : "uboot", in soc_clk_dump()
2296 priv->armclk_enter_hz / 1000, in soc_clk_dump()
2297 priv->armclk_init_hz / 1000, in soc_clk_dump()
2298 priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0, in soc_clk_dump()
2299 priv->set_armclk_rate ? " KHz" : "N/A"); in soc_clk_dump()
2302 if (clk_dump->name) { in soc_clk_dump()
2303 clk.id = clk_dump->id; in soc_clk_dump()
2304 if (clk_dump->is_cru) in soc_clk_dump()
2305 ret = clk_request(cru_dev, &clk); in soc_clk_dump()
2307 ret = clk_request(pmucru_dev, &clk); in soc_clk_dump()
2311 rate = clk_get_rate(&clk); in soc_clk_dump()
2312 clk_free(&clk); in soc_clk_dump()
2315 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
2318 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()
2322 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
2325 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()