Lines Matching refs:CLK_GENERAL
53 case CLK_GENERAL: in rv1108_pll_id()
150 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_mac_set_clk()
175 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_sfc_set_clk()
306 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_aclk_bus_get_clk()
318 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_aclk_bus_set_clk()
334 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_aclk_peri_get_clk()
346 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_hclk_peri_get_clk()
358 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_pclk_peri_get_clk()
370 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_aclk_peri_set_clk()
386 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_hclk_peri_set_clk()
401 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_pclk_peri_set_clk()
494 return DIV_TO_RATE(rkclk_pll_get_rate(cru, CLK_GENERAL), div); in rv1108_spi_get_clk()
501 div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, CLK_GENERAL), hz); in rv1108_spi_set_clk()
534 div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, CLK_GENERAL), rate); in rv1108_mmc_set_clk()
540 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_mmc_set_clk()
671 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); in rkclk_init()
679 gpll = rkclk_pll_get_rate(cru, CLK_GENERAL); in rkclk_init()