29 #define DIV_TO_RATE(input_rate, div)	((input_rate) / ((div) + 1))  argument
66 			 const struct pll_div *div)  in rkclk_set_pll()  argument
72 	uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;  in rkclk_set_pll()
73 	uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;  in rkclk_set_pll()
76 	      pll, div->fbdiv, div->refdiv, div->postdiv1,  in rkclk_set_pll()
77 	      div->postdiv2, vco_hz, output_hz);  in rkclk_set_pll()
93 	rk_clrsetreg(&pll->con0, FBDIV_MASK, div->fbdiv << FBDIV_SHIFT);  in rkclk_set_pll()
95 		     (div->postdiv1 << POSTDIV1_SHIFT |  in rkclk_set_pll()
96 		     div->postdiv2 << POSTDIV2_SHIFT |  in rkclk_set_pll()
97 		     div->refdiv << REFDIV_SHIFT));  in rkclk_set_pll()
99 		     (div->refdiv << REFDIV_SHIFT));  in rkclk_set_pll()
147 	uint8_t div;  in rv1108_mac_set_clk()  local
158 	div = DIV_ROUND_UP(pll_rate, rate) - 1;  in rv1108_mac_set_clk()
159 	if (div <= 0x1f)  in rv1108_mac_set_clk()
161 			     div << MAC_CLK_DIV_SHIFT);  in rv1108_mac_set_clk()
163 		debug("Unsupported div for gmac:%d\n", div);  in rv1108_mac_set_clk()
165 	return DIV_TO_RATE(pll_rate, div);  in rv1108_mac_set_clk()
172 	u32 div;  in rv1108_sfc_set_clk()  local
179 	div = DIV_ROUND_UP(pll_rate, rate) - 1;  in rv1108_sfc_set_clk()
180 	if (div <= 0x3f)  in rv1108_sfc_set_clk()
182 			     div << SFC_CLK_DIV_SHIFT);  in rv1108_sfc_set_clk()
186 	return DIV_TO_RATE(pll_rate, div);  in rv1108_sfc_set_clk()
191 	u32 div, val;  in rv1108_saradc_get_clk()  local
194 	div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,  in rv1108_saradc_get_clk()
197 	return DIV_TO_RATE(OSC_HZ, div);  in rv1108_saradc_get_clk()
216 	u32 div, val;  in rv1108_aclk_vio1_get_clk()  local
219 	div = bitfield_extract(val, ACLK_VIO1_CLK_DIV_SHIFT,  in rv1108_aclk_vio1_get_clk()
222 	return DIV_TO_RATE(GPLL_HZ, div);  in rv1108_aclk_vio1_get_clk()
242 	u32 div, val;  in rv1108_aclk_vio0_get_clk()  local
245 	div = bitfield_extract(val, ACLK_VIO0_CLK_DIV_SHIFT,  in rv1108_aclk_vio0_get_clk()
248 	return DIV_TO_RATE(GPLL_HZ, div);  in rv1108_aclk_vio0_get_clk()
263 	/*HCLK_VIO default div = 4*/  in rv1108_aclk_vio0_set_clk()
267 	/*PCLK_VIO default div = 4*/  in rv1108_aclk_vio0_set_clk()
277 	u32 div, val;  in rv1108_dclk_vop_get_clk()  local
280 	div = bitfield_extract(val, DCLK_VOP_CLK_DIV_SHIFT,  in rv1108_dclk_vop_get_clk()
283 	return DIV_TO_RATE(GPLL_HZ, div);  in rv1108_dclk_vop_get_clk()
305 	u32 div, val;  in rv1108_aclk_bus_get_clk()  local
309 	div = bitfield_extract(val, ACLK_BUS_DIV_CON_SHIFT,  in rv1108_aclk_bus_get_clk()
312 	return DIV_TO_RATE(parent_rate, div);  in rv1108_aclk_bus_get_clk()
333 	u32 div, val;  in rv1108_aclk_peri_get_clk()  local
337 	div = bitfield_extract(val, ACLK_PERI_DIV_CON_SHIFT,  in rv1108_aclk_peri_get_clk()
340 	return DIV_TO_RATE(parent_rate, div);  in rv1108_aclk_peri_get_clk()
345 	u32 div, val;  in rv1108_hclk_peri_get_clk()  local
349 	div = bitfield_extract(val, HCLK_PERI_DIV_CON_SHIFT,  in rv1108_hclk_peri_get_clk()
352 	return DIV_TO_RATE(parent_rate, div);  in rv1108_hclk_peri_get_clk()
357 	u32 div, val;  in rv1108_pclk_peri_get_clk()  local
361 	div = bitfield_extract(val, PCLK_PERI_DIV_CON_SHIFT,  in rv1108_pclk_peri_get_clk()
364 	return DIV_TO_RATE(parent_rate, div);  in rv1108_pclk_peri_get_clk()
415 	u32 div, con;  in rv1108_i2c_get_clk()  local
420 		div = bitfield_extract(con, CLK_I2C0_DIV_CON_SHIFT,  in rv1108_i2c_get_clk()
425 		div = bitfield_extract(con, CLK_I2C1_DIV_CON_SHIFT,  in rv1108_i2c_get_clk()
430 		div = bitfield_extract(con, CLK_I2C2_DIV_CON_SHIFT,  in rv1108_i2c_get_clk()
435 		div = bitfield_extract(con, CLK_I2C3_DIV_CON_SHIFT,  in rv1108_i2c_get_clk()
443 	return DIV_TO_RATE(GPLL_HZ, div);  in rv1108_i2c_get_clk()
489 	u32 div, con;  in rv1108_spi_get_clk()  local
492 	div = (con & SPI_DIV_MASK) >> SPI_DIV_SHIFT;  in rv1108_spi_get_clk()
494 	return DIV_TO_RATE(rkclk_pll_get_rate(cru, CLK_GENERAL), div);  in rv1108_spi_get_clk()
499 	int div;  in rv1108_spi_set_clk()  local
501 	div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, CLK_GENERAL), hz);  in rv1108_spi_set_clk()
502 	assert(div - 1 < 128);  in rv1108_spi_set_clk()
506 		     (div - 1) << SPI_DIV_SHIFT);  in rv1108_spi_set_clk()
512 	u32 div, con;  in rv1108_mmc_get_clk()  local
516 	div = bitfield_extract(con, EMMC_CLK_DIV_SHIFT, 8);  in rv1108_mmc_get_clk()
521 		mmc_clk = DIV_TO_RATE(OSC_HZ, div) / 2;  in rv1108_mmc_get_clk()
523 		mmc_clk = DIV_TO_RATE(GPLL_HZ, div) / 2;  in rv1108_mmc_get_clk()
525 	debug("%s div %d get_clk %ld\n", __func__, div, mmc_clk);  in rv1108_mmc_get_clk()
531 	int div;  in rv1108_mmc_set_clk()  local
534 	div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, CLK_GENERAL), rate);  in rv1108_mmc_set_clk()
536 	if (div < 127) {  in rv1108_mmc_set_clk()
548 	div = DIV_ROUND_UP(pll_rate / 2, rate);  in rv1108_mmc_set_clk()
550 		     ((div - 1) << EMMC_CLK_DIV_SHIFT));  in rv1108_mmc_set_clk()
552 	debug("%s set_rate %ld div %d\n", __func__,  rate, div);  in rv1108_mmc_set_clk()
554 	return DIV_TO_RATE(pll_rate, div);  in rv1108_mmc_set_clk()