Lines Matching +full:rv1106 +full:- +full:cru
1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Elaine Zhang <zhangqing@rock-chips.com>
9 #include <clk-uclass.h>
19 #include <dt-bindings/clock/rv1106-cru.h>
78 struct rv1106_cru *cru = priv->cru; in rv1106_peri_get_clk() local
83 con = readl(&cru->peri_clksel_con[1]); in rv1106_peri_get_clk()
95 con = readl(&cru->peri_clksel_con[1]); in rv1106_peri_get_clk()
107 con = readl(&cru->peri_clksel_con[1]); in rv1106_peri_get_clk()
117 con = readl(&cru->peri_clksel_con[9]); in rv1106_peri_get_clk()
129 con = readl(&cru->clksel_con[24]); in rv1106_peri_get_clk()
139 con = readl(&cru->pmu_clksel_con[0]); in rv1106_peri_get_clk()
147 con = readl(&cru->pmu_clksel_con[0]); in rv1106_peri_get_clk()
157 return -ENOENT; in rv1106_peri_get_clk()
166 struct rv1106_cru *cru = priv->cru; in rv1106_peri_set_clk() local
179 rk_clrsetreg(&cru->peri_clksel_con[1], in rv1106_peri_set_clk()
192 rk_clrsetreg(&cru->peri_clksel_con[1], in rv1106_peri_set_clk()
203 rk_clrsetreg(&cru->peri_clksel_con[1], in rv1106_peri_set_clk()
216 rk_clrsetreg(&cru->peri_clksel_con[9], in rv1106_peri_set_clk()
227 rk_clrsetreg(&cru->clksel_con[24], in rv1106_peri_set_clk()
236 rk_clrsetreg(&cru->pmu_clksel_con[0], in rv1106_peri_set_clk()
247 rk_clrsetreg(&cru->pmu_clksel_con[0], in rv1106_peri_set_clk()
253 return -EINVAL; in rv1106_peri_set_clk()
261 struct rv1106_cru *cru = priv->cru; in rv1106_i2c_get_clk() local
267 con = readl(&cru->pmu_clksel_con[0]); in rv1106_i2c_get_clk()
279 con = readl(&cru->peri_clksel_con[1]); in rv1106_i2c_get_clk()
283 con = readl(&cru->peri_clksel_con[1]); in rv1106_i2c_get_clk()
287 con = readl(&cru->peri_clksel_con[1]); in rv1106_i2c_get_clk()
291 con = readl(&cru->peri_clksel_con[2]); in rv1106_i2c_get_clk()
295 return -ENOENT; in rv1106_i2c_get_clk()
313 struct rv1106_cru *cru = priv->cru; in rv1106_crypto_get_clk() local
318 con = readl(&cru->peri_clksel_con[6]); in rv1106_crypto_get_clk()
323 con = readl(&cru->peri_clksel_con[6]); in rv1106_crypto_get_clk()
328 return -ENOENT; in rv1106_crypto_get_clk()
340 return -ENOENT; in rv1106_crypto_get_clk()
347 struct rv1106_cru *cru = priv->cru; in rv1106_crypto_set_clk() local
361 rk_clrsetreg(&cru->peri_clksel_con[6], in rv1106_crypto_set_clk()
366 rk_clrsetreg(&cru->peri_clksel_con[6], in rv1106_crypto_set_clk()
371 return -ENOENT; in rv1106_crypto_set_clk()
378 struct rv1106_cru *cru = priv->cru; in rv1106_mmc_get_clk() local
384 con = readl(&cru->vi_clksel_con[1]); in rv1106_mmc_get_clk()
396 con = readl(&cru->peri_clksel_con[7]); in rv1106_mmc_get_clk()
408 con = readl(&cru->peri_clksel_con[7]); in rv1106_mmc_get_clk()
423 return -ENOENT; in rv1106_mmc_get_clk()
430 struct rv1106_cru *cru = priv->cru; in rv1106_mmc_set_clk() local
454 rk_clrsetreg(&cru->vi_clksel_con[1], in rv1106_mmc_set_clk()
458 ((src_clk_div - 1) << in rv1106_mmc_set_clk()
471 rk_clrsetreg(&cru->peri_clksel_con[7], in rv1106_mmc_set_clk()
475 ((src_clk_div - 1) << in rv1106_mmc_set_clk()
494 rk_clrsetreg(&cru->peri_clksel_con[7], in rv1106_mmc_set_clk()
498 ((src_clk_div - 1) << in rv1106_mmc_set_clk()
502 return -ENOENT; in rv1106_mmc_set_clk()
511 struct rv1106_cru *cru = priv->cru; in rv1106_i2c_set_clk() local
533 rk_clrsetreg(&cru->clksel_con[71], CLK_I2C1_SEL_MASK, in rv1106_i2c_set_clk()
537 rk_clrsetreg(&cru->peri_clksel_con[1], CLK_I2C0_SEL_MASK, in rv1106_i2c_set_clk()
541 rk_clrsetreg(&cru->peri_clksel_con[1], CLK_I2C2_SEL_MASK, in rv1106_i2c_set_clk()
545 rk_clrsetreg(&cru->peri_clksel_con[1], CLK_I2C3_SEL_MASK, in rv1106_i2c_set_clk()
549 rk_clrsetreg(&cru->peri_clksel_con[2], CLK_I2C4_SEL_MASK, in rv1106_i2c_set_clk()
553 return -ENOENT; in rv1106_i2c_set_clk()
562 struct rv1106_cru *cru = priv->cru; in rv1106_spi_get_clk() local
567 con = readl(&cru->vepu_clksel_con[0]); in rv1106_spi_get_clk()
571 con = readl(&cru->peri_clksel_con[6]); in rv1106_spi_get_clk()
575 return -ENOENT; in rv1106_spi_get_clk()
592 struct rv1106_cru *cru = priv->cru; in rv1106_spi_set_clk() local
606 rk_clrsetreg(&cru->vepu_clksel_con[0], CLK_SPI0_SEL_MASK, in rv1106_spi_set_clk()
610 rk_clrsetreg(&cru->peri_clksel_con[6], CLK_SPI1_SEL_MASK, in rv1106_spi_set_clk()
614 return -ENOENT; in rv1106_spi_set_clk()
623 struct rv1106_cru *cru = priv->cru; in rv1106_pwm_get_clk() local
628 con = readl(&cru->peri_clksel_con[11]); in rv1106_pwm_get_clk()
632 con = readl(&cru->peri_clksel_con[6]); in rv1106_pwm_get_clk()
636 con = readl(&cru->peri_clksel_con[6]); in rv1106_pwm_get_clk()
640 return -ENOENT; in rv1106_pwm_get_clk()
651 return -ENOENT; in rv1106_pwm_get_clk()
658 struct rv1106_cru *cru = priv->cru; in rv1106_pwm_set_clk() local
670 rk_clrsetreg(&cru->peri_clksel_con[11], in rv1106_pwm_set_clk()
675 rk_clrsetreg(&cru->peri_clksel_con[6], in rv1106_pwm_set_clk()
680 rk_clrsetreg(&cru->peri_clksel_con[6], in rv1106_pwm_set_clk()
685 return -ENOENT; in rv1106_pwm_set_clk()
694 struct rv1106_cru *cru = priv->cru; in rv1106_adc_get_clk() local
699 con = readl(&cru->peri_clksel_con[6]); in rv1106_adc_get_clk()
704 con = readl(&cru->vo_clksel_con[3]); in rv1106_adc_get_clk()
709 con = readl(&cru->vo_clksel_con[3]); in rv1106_adc_get_clk()
713 return -ENOENT; in rv1106_adc_get_clk()
720 struct rv1106_cru *cru = priv->cru; in rv1106_adc_set_clk() local
727 assert(src_clk_div - 1 <= 7); in rv1106_adc_set_clk()
728 rk_clrsetreg(&cru->peri_clksel_con[6], in rv1106_adc_set_clk()
730 (src_clk_div - 1) << in rv1106_adc_set_clk()
734 assert(src_clk_div - 1 <= 128); in rv1106_adc_set_clk()
735 rk_clrsetreg(&cru->vo_clksel_con[3], in rv1106_adc_set_clk()
737 (src_clk_div - 1) << in rv1106_adc_set_clk()
741 assert(src_clk_div - 1 <= 128); in rv1106_adc_set_clk()
742 rk_clrsetreg(&cru->vo_clksel_con[3], in rv1106_adc_set_clk()
744 (src_clk_div - 1) << in rv1106_adc_set_clk()
748 return -ENOENT; in rv1106_adc_set_clk()
757 * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
807 struct rv1106_cru *cru = priv->cru; in rv1106_uart_get_rate() local
831 return -ENOENT; in rv1106_uart_get_rate()
833 con = readl(&cru->clksel_con[reg + 2]); in rv1106_uart_get_rate()
835 con = readl(&cru->clksel_con[reg]); in rv1106_uart_get_rate()
839 p_rate = priv->gpll_hz; in rv1106_uart_get_rate()
841 p_rate = priv->cpll_hz; in rv1106_uart_get_rate()
847 fracdiv = readl(&cru->clksel_con[reg + 1]); in rv1106_uart_get_rate()
861 struct rv1106_cru *cru = priv->cru; in rv1106_uart_set_rate() local
865 if (priv->gpll_hz % rate == 0) { in rv1106_uart_set_rate()
868 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1106_uart_set_rate()
869 } else if (priv->cpll_hz % rate == 0) { in rv1106_uart_set_rate()
872 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1106_uart_set_rate()
881 rational_best_approximation(rate, priv->gpll_hz / div, in rv1106_uart_set_rate()
882 GENMASK(16 - 1, 0), in rv1106_uart_set_rate()
883 GENMASK(16 - 1, 0), in rv1106_uart_set_rate()
907 return -ENOENT; in rv1106_uart_set_rate()
909 rk_clrsetreg(&cru->clksel_con[reg], in rv1106_uart_set_rate()
913 ((div - 1) << CLK_UART_SRC_DIV_SHIFT)); in rv1106_uart_set_rate()
914 rk_clrsetreg(&cru->clksel_con[reg + 2], in rv1106_uart_set_rate()
919 writel(val, &cru->clksel_con[reg + 1]); in rv1106_uart_set_rate()
927 struct rv1106_cru *cru = priv->cru; in rv1106_vop_get_clk() local
933 con = readl(&cru->vo_clksel_con[1]); in rv1106_vop_get_clk()
945 con = readl(&cru->clksel_con[23]); in rv1106_vop_get_clk()
949 return DIV_TO_RATE(priv->gpll_hz, div); in rv1106_vop_get_clk()
951 return DIV_TO_RATE(priv->cpll_hz, div); in rv1106_vop_get_clk()
953 return -ENOENT; in rv1106_vop_get_clk()
960 struct rv1106_cru *cru = priv->cru; in rv1106_vop_set_clk() local
974 rk_clrsetreg(&cru->vo_clksel_con[1], in rv1106_vop_set_clk()
980 if ((priv->cpll_hz % rate) == 0) { in rv1106_vop_set_clk()
982 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rv1106_vop_set_clk()
985 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1106_vop_set_clk()
987 rk_clrsetreg(&cru->clksel_con[23], in rv1106_vop_set_clk()
991 (div - 1) << DCLK_VOP_DIV_SHIFT); in rv1106_vop_set_clk()
994 return -ENOENT; in rv1106_vop_set_clk()
1002 struct rv1106_cru *cru = priv->cru; in rv1106_decom_get_clk() local
1005 con = readl(&cru->peri_clksel_con[7]); in rv1106_decom_get_clk()
1021 struct rv1106_cru *cru = priv->cru; in rv1106_decom_set_clk() local
1032 rk_clrsetreg(&cru->peri_clksel_con[7], DCLK_DECOM_SEL_MASK, in rv1106_decom_set_clk()
1041 struct rv1106_clk_priv *priv = dev_get_priv(clk->dev); in rv1106_clk_get_rate()
1044 if (!priv->gpll_hz) { in rv1106_clk_get_rate()
1045 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); in rv1106_clk_get_rate()
1046 return -ENOENT; in rv1106_clk_get_rate()
1049 switch (clk->id) { in rv1106_clk_get_rate()
1052 rate = rockchip_pll_get_rate(&rv1106_pll_clks[APLL], priv->cru, in rv1106_clk_get_rate()
1056 rate = rockchip_pll_get_rate(&rv1106_pll_clks[DPLL], priv->cru, in rv1106_clk_get_rate()
1060 rate = rockchip_pll_get_rate(&rv1106_pll_clks[CPLL], priv->cru, in rv1106_clk_get_rate()
1064 rate = rockchip_pll_get_rate(&rv1106_pll_clks[GPLL], priv->cru, in rv1106_clk_get_rate()
1074 rate = rv1106_peri_get_clk(priv, clk->id); in rv1106_clk_get_rate()
1080 rate = rv1106_crypto_get_clk(priv, clk->id); in rv1106_clk_get_rate()
1088 rate = rv1106_mmc_get_clk(priv, clk->id); in rv1106_clk_get_rate()
1096 rate = rv1106_i2c_get_clk(priv, clk->id); in rv1106_clk_get_rate()
1101 rate = rv1106_spi_get_clk(priv, clk->id); in rv1106_clk_get_rate()
1107 rate = rv1106_pwm_get_clk(priv, clk->id); in rv1106_clk_get_rate()
1113 rate = rv1106_adc_get_clk(priv, clk->id); in rv1106_clk_get_rate()
1122 rate = rv1106_uart_get_rate(priv, clk->id); in rv1106_clk_get_rate()
1128 rate = rv1106_vop_get_clk(priv, clk->id); in rv1106_clk_get_rate()
1135 return -ENOENT; in rv1106_clk_get_rate()
1143 struct rv1106_clk_priv *priv = dev_get_priv(clk->dev); in rv1106_clk_set_rate()
1146 if (!priv->gpll_hz) { in rv1106_clk_set_rate()
1147 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); in rv1106_clk_set_rate()
1148 return -ENOENT; in rv1106_clk_set_rate()
1151 switch (clk->id) { in rv1106_clk_set_rate()
1154 ret = rockchip_pll_set_rate(&rv1106_pll_clks[APLL], priv->cru, in rv1106_clk_set_rate()
1158 ret = rockchip_pll_set_rate(&rv1106_pll_clks[CPLL], priv->cru, in rv1106_clk_set_rate()
1162 ret = rockchip_pll_set_rate(&rv1106_pll_clks[GPLL], priv->cru, in rv1106_clk_set_rate()
1172 ret = rv1106_peri_set_clk(priv, clk->id, rate); in rv1106_clk_set_rate()
1178 ret = rv1106_crypto_set_clk(priv, clk->id, rate); in rv1106_clk_set_rate()
1186 ret = rv1106_mmc_set_clk(priv, clk->id, rate); in rv1106_clk_set_rate()
1194 ret = rv1106_i2c_set_clk(priv, clk->id, rate); in rv1106_clk_set_rate()
1199 ret = rv1106_spi_set_clk(priv, clk->id, rate); in rv1106_clk_set_rate()
1205 ret = rv1106_pwm_set_clk(priv, clk->id, rate); in rv1106_clk_set_rate()
1211 ret = rv1106_adc_set_clk(priv, clk->id, rate); in rv1106_clk_set_rate()
1220 ret = rv1106_uart_set_rate(priv, clk->id, rate); in rv1106_clk_set_rate()
1226 rate = rv1106_vop_set_clk(priv, clk->id, rate); in rv1106_clk_set_rate()
1233 return -ENOENT; in rv1106_clk_set_rate()
1241 switch (clk->id) { in rv1106_clk_set_parent()
1243 return -ENOENT; in rv1106_clk_set_parent()
1262 priv->sync_kernel = false; in rv1106_clk_init()
1263 if (!priv->armclk_enter_hz) { in rv1106_clk_init()
1264 priv->armclk_enter_hz = in rv1106_clk_init()
1266 priv->cru, APLL); in rv1106_clk_init()
1267 priv->armclk_init_hz = priv->armclk_enter_hz; in rv1106_clk_init()
1270 if (priv->armclk_init_hz != APLL_HZ) { in rv1106_clk_init()
1271 ret = rockchip_pll_set_rate(&rv1106_pll_clks[APLL], priv->cru, in rv1106_clk_init()
1274 priv->armclk_init_hz = APLL_HZ; in rv1106_clk_init()
1277 if (priv->cpll_hz != CPLL_HZ) { in rv1106_clk_init()
1278 ret = rockchip_pll_set_rate(&rv1106_pll_clks[CPLL], priv->cru, in rv1106_clk_init()
1281 priv->cpll_hz = CPLL_HZ; in rv1106_clk_init()
1284 if (priv->gpll_hz != GPLL_HZ) { in rv1106_clk_init()
1285 ret = rockchip_pll_set_rate(&rv1106_pll_clks[GPLL], priv->cru, in rv1106_clk_init()
1288 priv->gpll_hz = GPLL_HZ; in rv1106_clk_init()
1301 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ in rv1106_clk_probe()
1306 priv->sync_kernel = true; in rv1106_clk_probe()
1308 priv->gpll_hz = GPLL_HZ; in rv1106_clk_probe()
1309 priv->cpll_hz = CPLL_HZ; in rv1106_clk_probe()
1311 rk_clrsetreg(&priv->cru->core_clksel_con[0], in rv1106_clk_probe()
1326 priv->cru = dev_read_addr_ptr(dev); in rv1106_clk_ofdata_to_platdata()
1345 priv->glb_srst_fst_value = offsetof(struct rv1106_cru, in rv1106_clk_bind()
1347 priv->glb_srst_snd_value = offsetof(struct rv1106_cru, in rv1106_clk_bind()
1349 sys_child->priv = priv; in rv1106_clk_bind()
1358 sf_priv->sf_reset_offset = offsetof(struct rv1106_cru, in rv1106_clk_bind()
1360 sf_priv->sf_reset_num = 31745; in rv1106_clk_bind()
1361 sf_child->priv = sf_priv; in rv1106_clk_bind()
1368 { .compatible = "rockchip,rv1106-cru" },
1394 printf("%s: could not find cru device\n", __func__); in rv1106_grfclk_get_rate()
1399 switch (clk->id) { in rv1106_grfclk_get_rate()
1410 return -ENOENT; in rv1106_grfclk_get_rate()
1423 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
1430 struct rv1106_grf_clk_priv *priv = dev_get_priv(clk->dev); in rv1106_mmc_get_phase()
1439 if (clk->id == SCLK_EMMC_SAMPLE) in rv1106_mmc_get_phase()
1440 raw_value = readl(&priv->grf->emmc_con1); in rv1106_mmc_get_phase()
1441 else if (clk->id == SCLK_SDMMC_SAMPLE) in rv1106_mmc_get_phase()
1442 raw_value = readl(&priv->grf->sdmmc_con1); in rv1106_mmc_get_phase()
1443 else if (clk->id == SCLK_SDIO_SAMPLE) in rv1106_mmc_get_phase()
1444 raw_value = readl(&priv->grf->sdio_con1); in rv1106_mmc_get_phase()
1464 struct rv1106_grf_clk_priv *priv = dev_get_priv(clk->dev); in rv1106_mmc_set_phase()
1478 * don't overflow 32-bit / 64-bit numbers. in rv1106_mmc_set_phase()
1492 if (clk->id == SCLK_EMMC_SAMPLE) in rv1106_mmc_set_phase()
1493 writel(raw_value | 0xffff0000, &priv->grf->emmc_con1); in rv1106_mmc_set_phase()
1494 else if (clk->id == SCLK_SDMMC_SAMPLE) in rv1106_mmc_set_phase()
1495 writel(raw_value | 0xffff0000, &priv->grf->sdmmc_con1); in rv1106_mmc_set_phase()
1496 else if (clk->id == SCLK_SDIO_SAMPLE) in rv1106_mmc_set_phase()
1497 writel(raw_value | 0xffff0000, &priv->grf->sdio_con1); in rv1106_mmc_set_phase()
1509 debug("%s %ld\n", __func__, clk->id); in rv1106_grfclk_get_phase()
1510 switch (clk->id) { in rv1106_grfclk_get_phase()
1517 return -ENOENT; in rv1106_grfclk_get_phase()
1526 debug("%s %ld\n", __func__, clk->id); in rv1106_grfclk_set_phase()
1527 switch (clk->id) { in rv1106_grfclk_set_phase()
1534 return -ENOENT; in rv1106_grfclk_set_phase()
1550 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rv1106_grfclk_probe()
1551 if (IS_ERR(priv->grf)) in rv1106_grfclk_probe()
1552 return PTR_ERR(priv->grf); in rv1106_grfclk_probe()
1568 { .compatible = "rockchip,rv1106-grf-cru" },
1585 * soc_clk_dump() - Print clock frequencies
1604 printf("%s failed to get cru device\n", __func__); in soc_clk_dump()
1610 priv->sync_kernel ? "sync kernel" : "uboot", in soc_clk_dump()
1611 priv->armclk_enter_hz / 1000, in soc_clk_dump()
1612 priv->armclk_init_hz / 1000, in soc_clk_dump()
1613 priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0, in soc_clk_dump()
1614 priv->set_armclk_rate ? " KHz" : "N/A"); in soc_clk_dump()
1617 if (clk_dump->name) { in soc_clk_dump()
1618 clk.id = clk_dump->id; in soc_clk_dump()
1619 if (clk_dump->is_cru) in soc_clk_dump()
1628 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
1631 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()
1635 printf(" %s %s\n", clk_dump->name, in soc_clk_dump()
1638 printf(" %s %lu KHz\n", clk_dump->name, in soc_clk_dump()