Lines Matching full:rate
79 u32 con, sel, rate; in rv1106_peri_get_clk() local
86 rate = 400 * MHz; in rv1106_peri_get_clk()
88 rate = 200 * MHz; in rv1106_peri_get_clk()
90 rate = 100 * MHz; in rv1106_peri_get_clk()
92 rate = OSC_HZ; in rv1106_peri_get_clk()
98 rate = 200 * MHz; in rv1106_peri_get_clk()
100 rate = 100 * MHz; in rv1106_peri_get_clk()
102 rate = 50 * MHz; in rv1106_peri_get_clk()
104 rate = OSC_HZ; in rv1106_peri_get_clk()
110 rate = 100 * MHz; in rv1106_peri_get_clk()
112 rate = 50 * MHz; in rv1106_peri_get_clk()
114 rate = OSC_HZ; in rv1106_peri_get_clk()
120 rate = 300 * MHz; in rv1106_peri_get_clk()
122 rate = 200 * MHz; in rv1106_peri_get_clk()
124 rate = 100 * MHz; in rv1106_peri_get_clk()
126 rate = OSC_HZ; in rv1106_peri_get_clk()
132 rate = 100 * MHz; in rv1106_peri_get_clk()
134 rate = 50 * MHz; in rv1106_peri_get_clk()
136 rate = OSC_HZ; in rv1106_peri_get_clk()
142 rate = 100 * MHz; in rv1106_peri_get_clk()
144 rate = OSC_HZ; in rv1106_peri_get_clk()
150 rate = 200 * MHz; in rv1106_peri_get_clk()
152 rate = 100 * MHz; in rv1106_peri_get_clk()
154 rate = OSC_HZ; in rv1106_peri_get_clk()
160 return rate; in rv1106_peri_get_clk()
164 ulong clk_id, ulong rate) in rv1106_peri_set_clk() argument
171 if (rate >= 396 * MHz) in rv1106_peri_set_clk()
173 else if (rate >= 198 * MHz) in rv1106_peri_set_clk()
175 else if (rate >= 99 * MHz) in rv1106_peri_set_clk()
184 if (rate >= 198 * MHz) in rv1106_peri_set_clk()
186 else if (rate >= 99 * MHz) in rv1106_peri_set_clk()
188 else if (rate >= 48 * MHz) in rv1106_peri_set_clk()
197 if (rate >= 99 * MHz) in rv1106_peri_set_clk()
199 else if (rate >= 48 * MHz) in rv1106_peri_set_clk()
208 if (rate >= 297 * MHz) in rv1106_peri_set_clk()
210 else if (rate >= 198 * MHz) in rv1106_peri_set_clk()
212 else if (rate >= 99 * MHz) in rv1106_peri_set_clk()
221 if (rate >= 99 * MHz) in rv1106_peri_set_clk()
223 else if (rate >= 48 * MHz) in rv1106_peri_set_clk()
232 if (rate >= 99 * MHz) in rv1106_peri_set_clk()
241 if (rate >= 198 * MHz) in rv1106_peri_set_clk()
243 else if (rate >= 99 * MHz) in rv1106_peri_set_clk()
263 ulong rate; in rv1106_i2c_get_clk() local
270 rate = 200 * MHz; in rv1106_i2c_get_clk()
272 rate = 100 * MHz; in rv1106_i2c_get_clk()
274 rate = OSC_HZ; in rv1106_i2c_get_clk()
276 rate = 32768; in rv1106_i2c_get_clk()
277 return rate; in rv1106_i2c_get_clk()
299 rate = 200 * MHz; in rv1106_i2c_get_clk()
301 rate = 100 * MHz; in rv1106_i2c_get_clk()
303 rate = 50 * MHz; in rv1106_i2c_get_clk()
305 rate = OSC_HZ; in rv1106_i2c_get_clk()
307 return rate; in rv1106_i2c_get_clk()
345 ulong clk_id, ulong rate) in rv1106_crypto_set_clk() argument
350 if (rate >= 297 * MHz) in rv1106_crypto_set_clk()
352 else if (rate >= 198 * MHz) in rv1106_crypto_set_clk()
354 else if (rate >= 99 * MHz) in rv1106_crypto_set_clk()
428 ulong clk_id, ulong rate) in rv1106_mmc_set_clk() argument
434 if ((OSC_HZ % rate) == 0) { in rv1106_mmc_set_clk()
441 src_clk_div = DIV_ROUND_UP(prate, rate); in rv1106_mmc_set_clk()
446 if ((OSC_HZ % rate) == 0) { in rv1106_mmc_set_clk()
453 src_clk_div = DIV_ROUND_UP(prate, rate); in rv1106_mmc_set_clk()
463 if ((OSC_HZ % rate) == 0) { in rv1106_mmc_set_clk()
470 src_clk_div = DIV_ROUND_UP(prate, rate); in rv1106_mmc_set_clk()
480 if ((OSC_HZ % rate) == 0) { in rv1106_mmc_set_clk()
483 } else if ((500 * MHz % rate) == 0) { in rv1106_mmc_set_clk()
486 } else if ((300 * MHz % rate) == 0) { in rv1106_mmc_set_clk()
493 src_clk_div = DIV_ROUND_UP(prate, rate); in rv1106_mmc_set_clk()
509 ulong rate) in rv1106_i2c_set_clk() argument
514 if (rate >= 198 * MHz) in rv1106_i2c_set_clk()
516 else if (rate >= 99 * MHz) in rv1106_i2c_set_clk()
518 else if (rate >= 48 * MHz) in rv1106_i2c_set_clk()
525 if (rate >= 198 * MHz) in rv1106_i2c_set_clk()
527 else if (rate >= 99 * MHz) in rv1106_i2c_set_clk()
529 else if (rate >= 24 * MHz) in rv1106_i2c_set_clk()
563 u32 sel, con, rate; in rv1106_spi_get_clk() local
578 rate = 200 * MHz; in rv1106_spi_get_clk()
580 rate = 100 * MHz; in rv1106_spi_get_clk()
582 rate = 50 * MHz; in rv1106_spi_get_clk()
584 rate = OSC_HZ; in rv1106_spi_get_clk()
586 return rate; in rv1106_spi_get_clk()
590 ulong clk_id, ulong rate) in rv1106_spi_set_clk() argument
595 if (rate >= 198 * MHz) in rv1106_spi_set_clk()
597 else if (rate >= 99 * MHz) in rv1106_spi_set_clk()
599 else if (rate >= 48 * MHz) in rv1106_spi_set_clk()
656 ulong clk_id, ulong rate) in rv1106_pwm_set_clk() argument
661 if (rate >= 99 * MHz) in rv1106_pwm_set_clk()
663 else if (rate >= 48 * MHz) in rv1106_pwm_set_clk()
718 ulong clk_id, ulong rate) in rv1106_adc_set_clk() argument
723 src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); in rv1106_adc_set_clk()
859 ulong clk_id, ulong rate) in rv1106_uart_set_rate() argument
865 if (priv->gpll_hz % rate == 0) { in rv1106_uart_set_rate()
868 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1106_uart_set_rate()
869 } else if (priv->cpll_hz % rate == 0) { in rv1106_uart_set_rate()
872 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1106_uart_set_rate()
873 } else if (rate == OSC_HZ) { in rv1106_uart_set_rate()
881 rational_best_approximation(rate, priv->gpll_hz / div, in rv1106_uart_set_rate()
958 ulong clk_id, ulong rate) in rv1106_vop_set_clk() argument
966 if (rate >= 297 * MHz) in rv1106_vop_set_clk()
968 else if (rate >= 198 * MHz) in rv1106_vop_set_clk()
970 else if (rate >= 99 * MHz) in rv1106_vop_set_clk()
980 if ((priv->cpll_hz % rate) == 0) { in rv1106_vop_set_clk()
982 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rv1106_vop_set_clk()
985 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1106_vop_set_clk()
1019 static ulong rv1106_decom_set_clk(struct rv1106_clk_priv *priv, ulong rate) in rv1106_decom_set_clk() argument
1024 if (rate >= 396 * MHz) in rv1106_decom_set_clk()
1026 else if (rate >= 198 * MHz) in rv1106_decom_set_clk()
1028 else if (rate >= 99 * MHz) in rv1106_decom_set_clk()
1042 ulong rate = 0; in rv1106_clk_get_rate() local
1052 rate = rockchip_pll_get_rate(&rv1106_pll_clks[APLL], priv->cru, in rv1106_clk_get_rate()
1056 rate = rockchip_pll_get_rate(&rv1106_pll_clks[DPLL], priv->cru, in rv1106_clk_get_rate()
1060 rate = rockchip_pll_get_rate(&rv1106_pll_clks[CPLL], priv->cru, in rv1106_clk_get_rate()
1064 rate = rockchip_pll_get_rate(&rv1106_pll_clks[GPLL], priv->cru, in rv1106_clk_get_rate()
1074 rate = rv1106_peri_get_clk(priv, clk->id); in rv1106_clk_get_rate()
1080 rate = rv1106_crypto_get_clk(priv, clk->id); in rv1106_clk_get_rate()
1088 rate = rv1106_mmc_get_clk(priv, clk->id); in rv1106_clk_get_rate()
1096 rate = rv1106_i2c_get_clk(priv, clk->id); in rv1106_clk_get_rate()
1101 rate = rv1106_spi_get_clk(priv, clk->id); in rv1106_clk_get_rate()
1107 rate = rv1106_pwm_get_clk(priv, clk->id); in rv1106_clk_get_rate()
1113 rate = rv1106_adc_get_clk(priv, clk->id); in rv1106_clk_get_rate()
1122 rate = rv1106_uart_get_rate(priv, clk->id); in rv1106_clk_get_rate()
1128 rate = rv1106_vop_get_clk(priv, clk->id); in rv1106_clk_get_rate()
1131 rate = rv1106_decom_get_clk(priv); in rv1106_clk_get_rate()
1138 return rate; in rv1106_clk_get_rate()
1141 static ulong rv1106_clk_set_rate(struct clk *clk, ulong rate) in rv1106_clk_set_rate() argument
1155 APLL, rate); in rv1106_clk_set_rate()
1159 CPLL, rate); in rv1106_clk_set_rate()
1163 GPLL, rate); in rv1106_clk_set_rate()
1172 ret = rv1106_peri_set_clk(priv, clk->id, rate); in rv1106_clk_set_rate()
1178 ret = rv1106_crypto_set_clk(priv, clk->id, rate); in rv1106_clk_set_rate()
1186 ret = rv1106_mmc_set_clk(priv, clk->id, rate); in rv1106_clk_set_rate()
1194 ret = rv1106_i2c_set_clk(priv, clk->id, rate); in rv1106_clk_set_rate()
1199 ret = rv1106_spi_set_clk(priv, clk->id, rate); in rv1106_clk_set_rate()
1205 ret = rv1106_pwm_set_clk(priv, clk->id, rate); in rv1106_clk_set_rate()
1211 ret = rv1106_adc_set_clk(priv, clk->id, rate); in rv1106_clk_set_rate()
1220 ret = rv1106_uart_set_rate(priv, clk->id, rate); in rv1106_clk_set_rate()
1226 rate = rv1106_vop_set_clk(priv, clk->id, rate); in rv1106_clk_set_rate()
1229 rate = rv1106_decom_set_clk(priv, rate); in rv1106_clk_set_rate()
1388 ulong rate = 0; in rv1106_grfclk_get_rate() local
1401 rate = rv1106_mmc_get_clk(cru_priv, CCLK_SRC_EMMC) / 2; in rv1106_grfclk_get_rate()
1404 rate = rv1106_mmc_get_clk(cru_priv, CCLK_SRC_SDMMC) / 2; in rv1106_grfclk_get_rate()
1407 rate = rv1106_mmc_get_clk(cru_priv, CCLK_SRC_SDIO) / 2; in rv1106_grfclk_get_rate()
1413 return rate; in rv1106_grfclk_get_rate()
1433 ulong rate; in rv1106_mmc_get_phase() local
1435 rate = rv1106_grfclk_get_rate(clk); in rv1106_mmc_get_phase()
1436 if (rate < 0) in rv1106_mmc_get_phase()
1437 return rate; in rv1106_mmc_get_phase()
1452 36 * (rate / 1000000); in rv1106_mmc_get_phase()
1467 ulong rate; in rv1106_mmc_set_phase() local
1469 rate = rv1106_grfclk_get_rate(clk); in rv1106_mmc_set_phase()
1470 if (rate < 0) in rv1106_mmc_set_phase()
1471 return rate; in rv1106_mmc_set_phase()
1482 delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 * in rv1106_mmc_set_phase()
1597 unsigned long rate; in soc_clk_dump() local
1624 rate = clk_get_rate(&clk); in soc_clk_dump()
1627 if (rate < 0) in soc_clk_dump()
1632 rate / 1000); in soc_clk_dump()
1634 if (rate < 0) in soc_clk_dump()
1639 rate / 1000); in soc_clk_dump()