153 	u32 con, sel, rate;  in rk3588_center_get_clk()  local
158 		sel = (con & ACLK_CENTER_ROOT_SEL_MASK) >>  in rk3588_center_get_clk()
160 		if (sel == ACLK_CENTER_ROOT_SEL_700M)  in rk3588_center_get_clk()
162 		else if (sel == ACLK_CENTER_ROOT_SEL_400M)  in rk3588_center_get_clk()
164 		else if (sel == ACLK_CENTER_ROOT_SEL_200M)  in rk3588_center_get_clk()
171 		sel = (con & ACLK_CENTER_LOW_ROOT_SEL_MASK) >>  in rk3588_center_get_clk()
173 		if (sel == ACLK_CENTER_LOW_ROOT_SEL_500M)  in rk3588_center_get_clk()
175 		else if (sel == ACLK_CENTER_LOW_ROOT_SEL_250M)  in rk3588_center_get_clk()
177 		else if (sel == ACLK_CENTER_LOW_ROOT_SEL_100M)  in rk3588_center_get_clk()
184 		sel = (con & HCLK_CENTER_ROOT_SEL_MASK) >>  in rk3588_center_get_clk()
186 		if (sel == HCLK_CENTER_ROOT_SEL_400M)  in rk3588_center_get_clk()
188 		else if (sel == HCLK_CENTER_ROOT_SEL_200M)  in rk3588_center_get_clk()
190 		else if (sel == HCLK_CENTER_ROOT_SEL_100M)  in rk3588_center_get_clk()
197 		sel = (con & PCLK_CENTER_ROOT_SEL_MASK) >>  in rk3588_center_get_clk()
199 		if (sel == PCLK_CENTER_ROOT_SEL_200M)  in rk3588_center_get_clk()
201 		else if (sel == PCLK_CENTER_ROOT_SEL_100M)  in rk3588_center_get_clk()
203 		else if (sel == PCLK_CENTER_ROOT_SEL_50M)  in rk3588_center_get_clk()
285 	u32 con, sel, div, rate, prate;  in rk3588_top_get_clk()  local
292 		sel = (con & ACLK_TOP_ROOT_SRC_SEL_MASK) >>  in rk3588_top_get_clk()
294 		if (sel == ACLK_TOP_ROOT_SRC_SEL_CPLL)  in rk3588_top_get_clk()
303 		sel = (con & ACLK_LOW_TOP_ROOT_SRC_SEL_MASK) >>  in rk3588_top_get_clk()
305 		if (sel == ACLK_LOW_TOP_ROOT_SRC_SEL_CPLL)  in rk3588_top_get_clk()
312 		sel = (con & PCLK_TOP_ROOT_SEL_MASK) >> PCLK_TOP_ROOT_SEL_SHIFT;  in rk3588_top_get_clk()
313 		if (sel == PCLK_TOP_ROOT_SEL_100M)  in rk3588_top_get_clk()
315 		else if (sel == PCLK_TOP_ROOT_SEL_50M)  in rk3588_top_get_clk()
382 	u32 sel, con;  in rk3588_i2c_get_clk()  local
388 		sel = (con & CLK_I2C0_SEL_MASK) >> CLK_I2C0_SEL_SHIFT;  in rk3588_i2c_get_clk()
392 		sel = (con & CLK_I2C1_SEL_MASK) >> CLK_I2C1_SEL_SHIFT;  in rk3588_i2c_get_clk()
396 		sel = (con & CLK_I2C2_SEL_MASK) >> CLK_I2C2_SEL_SHIFT;  in rk3588_i2c_get_clk()
400 		sel = (con & CLK_I2C3_SEL_MASK) >> CLK_I2C3_SEL_SHIFT;  in rk3588_i2c_get_clk()
404 		sel = (con & CLK_I2C4_SEL_MASK) >> CLK_I2C4_SEL_SHIFT;  in rk3588_i2c_get_clk()
408 		sel = (con & CLK_I2C5_SEL_MASK) >> CLK_I2C5_SEL_SHIFT;  in rk3588_i2c_get_clk()
412 		sel = (con & CLK_I2C6_SEL_MASK) >> CLK_I2C6_SEL_SHIFT;  in rk3588_i2c_get_clk()
416 		sel = (con & CLK_I2C7_SEL_MASK) >> CLK_I2C7_SEL_SHIFT;  in rk3588_i2c_get_clk()
420 		sel = (con & CLK_I2C8_SEL_MASK) >> CLK_I2C8_SEL_SHIFT;  in rk3588_i2c_get_clk()
425 	if (sel == CLK_I2C_SEL_200M)  in rk3588_i2c_get_clk()
491 	u32 sel, con;  in rk3588_spi_get_clk()  local
497 		sel = (con & CLK_SPI0_SEL_MASK) >> CLK_SPI0_SEL_SHIFT;  in rk3588_spi_get_clk()
500 		sel = (con & CLK_SPI1_SEL_MASK) >> CLK_SPI1_SEL_SHIFT;  in rk3588_spi_get_clk()
503 		sel = (con & CLK_SPI2_SEL_MASK) >> CLK_SPI2_SEL_SHIFT;  in rk3588_spi_get_clk()
506 		sel = (con & CLK_SPI3_SEL_MASK) >> CLK_SPI3_SEL_SHIFT;  in rk3588_spi_get_clk()
509 		sel = (con & CLK_SPI4_SEL_MASK) >> CLK_SPI4_SEL_SHIFT;  in rk3588_spi_get_clk()
515 	switch (sel) {  in rk3588_spi_get_clk()
576 	u32 sel, con;  in rk3588_pwm_get_clk()  local
581 		sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT;  in rk3588_pwm_get_clk()
585 		sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT;  in rk3588_pwm_get_clk()
589 		sel = (con & CLK_PWM3_SEL_MASK) >> CLK_PWM3_SEL_SHIFT;  in rk3588_pwm_get_clk()
593 		sel = (con & CLK_PMU1PWM_SEL_MASK) >> CLK_PMU1PWM_SEL_SHIFT;  in rk3588_pwm_get_clk()
599 	switch (sel) {  in rk3588_pwm_get_clk()
655 	u32 div, sel, con, prate;  in rk3588_adc_get_clk()  local
661 		sel = (con & CLK_SARADC_SEL_MASK) >>  in rk3588_adc_get_clk()
663 		if (sel == CLK_SARADC_SEL_24M)  in rk3588_adc_get_clk()
672 		sel = (con & CLK_TSADC_SEL_MASK) >>  in rk3588_adc_get_clk()
674 		if (sel == CLK_TSADC_SEL_24M)  in rk3588_adc_get_clk()
746 	u32 sel, con, div, prate;  in rk3588_mmc_get_clk()  local
752 		sel = (con & CCLK_SDIO_SRC_SEL_MASK) >>  in rk3588_mmc_get_clk()
754 		if (sel == CCLK_SDIO_SRC_SEL_GPLL)  in rk3588_mmc_get_clk()
756 		else if (sel == CCLK_SDIO_SRC_SEL_CPLL)  in rk3588_mmc_get_clk()
764 		sel = (con & CCLK_EMMC_SEL_MASK) >>  in rk3588_mmc_get_clk()
766 		if (sel == CCLK_EMMC_SEL_GPLL)  in rk3588_mmc_get_clk()
768 		else if (sel == CCLK_EMMC_SEL_CPLL)  in rk3588_mmc_get_clk()
776 		sel = (con & BCLK_EMMC_SEL_MASK) >>  in rk3588_mmc_get_clk()
778 		if (sel == CCLK_EMMC_SEL_CPLL)  in rk3588_mmc_get_clk()
786 		sel = (con & SCLK_SFC_SEL_MASK) >>  in rk3588_mmc_get_clk()
788 		if (sel == SCLK_SFC_SEL_GPLL)  in rk3588_mmc_get_clk()
790 		else if (sel == SCLK_SFC_SEL_CPLL)  in rk3588_mmc_get_clk()
798 		sel = (con & DCLK_DECOM_SEL_MASK) >>  in rk3588_mmc_get_clk()
800 		if (sel == DCLK_DECOM_SEL_SPLL)  in rk3588_mmc_get_clk()
949 	u32 div, sel, con, parent;  in rk3588_aclk_vop_get_clk()  local
956 		sel = (con & ACLK_VOP_ROOT_SEL_MASK) >> ACLK_VOP_ROOT_SEL_SHIFT;  in rk3588_aclk_vop_get_clk()
957 		if (sel == ACLK_VOP_ROOT_SEL_GPLL)  in rk3588_aclk_vop_get_clk()
959 		else if (sel == ACLK_VOP_ROOT_SEL_CPLL)  in rk3588_aclk_vop_get_clk()
961 		else if (sel == ACLK_VOP_ROOT_SEL_AUPLL)  in rk3588_aclk_vop_get_clk()
963 		else if (sel == ACLK_VOP_ROOT_SEL_NPLL)  in rk3588_aclk_vop_get_clk()
970 		sel = (con & ACLK_VOP_LOW_ROOT_SEL_MASK) >>  in rk3588_aclk_vop_get_clk()
972 		if (sel == ACLK_VOP_LOW_ROOT_SEL_400M)  in rk3588_aclk_vop_get_clk()
974 		else if (sel == ACLK_VOP_LOW_ROOT_SEL_200M)  in rk3588_aclk_vop_get_clk()
976 		else if (sel == ACLK_VOP_LOW_ROOT_SEL_100M)  in rk3588_aclk_vop_get_clk()
982 		sel = (con & HCLK_VOP_ROOT_SEL_MASK) >> HCLK_VOP_ROOT_SEL_SHIFT;  in rk3588_aclk_vop_get_clk()
983 		if (sel == HCLK_VOP_ROOT_SEL_200M)  in rk3588_aclk_vop_get_clk()
985 		else if (sel == HCLK_VOP_ROOT_SEL_100M)  in rk3588_aclk_vop_get_clk()
987 		else if (sel == HCLK_VOP_ROOT_SEL_50M)  in rk3588_aclk_vop_get_clk()
1063 	u32 div, sel, con, parent;  in rk3588_dclk_vop_get_clk()  local
1070 		sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT;  in rk3588_dclk_vop_get_clk()
1076 		sel = (con & DCLK1_VOP_SRC_SEL_MASK) >> DCLK1_VOP_SRC_SEL_SHIFT;  in rk3588_dclk_vop_get_clk()
1082 		sel = (con & DCLK2_VOP_SRC_SEL_MASK) >> DCLK2_VOP_SRC_SEL_SHIFT;  in rk3588_dclk_vop_get_clk()
1087 		sel = (con & DCLK3_VOP_SRC_SEL_MASK) >> DCLK3_VOP_SRC_SEL_SHIFT;  in rk3588_dclk_vop_get_clk()
1093 	if (sel == DCLK_VOP_SRC_SEL_AUPLL)  in rk3588_dclk_vop_get_clk()
1095 	else if (sel == DCLK_VOP_SRC_SEL_V0PLL)  in rk3588_dclk_vop_get_clk()
1098 	else if (sel == DCLK_VOP_SRC_SEL_GPLL)  in rk3588_dclk_vop_get_clk()
1113 	u32 i, conid, con, sel, div, best_div = 0, best_sel = 0;  in rk3588_dclk_vop_set_clk()  local
1121 		sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT;  in rk3588_dclk_vop_set_clk()
1130 		sel = (con & DCLK1_VOP_SRC_SEL_MASK) >> DCLK1_VOP_SRC_SEL_SHIFT;  in rk3588_dclk_vop_set_clk()
1139 		sel = (con & DCLK2_VOP_SRC_SEL_MASK) >> DCLK2_VOP_SRC_SEL_SHIFT;  in rk3588_dclk_vop_set_clk()
1147 		sel = (con & DCLK3_VOP_SRC_SEL_MASK) >> DCLK3_VOP_SRC_SEL_SHIFT;  in rk3588_dclk_vop_set_clk()
1156 	if (sel == DCLK_VOP_SRC_SEL_V0PLL) {  in rk3588_dclk_vop_set_clk()
1928 	u32 sel;  in rk3588_dclk_vop_set_parent()  local
1932 		sel = 2;  in rk3588_dclk_vop_set_parent()
1934 		sel = 0;  in rk3588_dclk_vop_set_parent()
1936 		sel = 1;  in rk3588_dclk_vop_set_parent()
1938 		sel = 3;  in rk3588_dclk_vop_set_parent()
1943 			     sel << DCLK0_VOP_SRC_SEL_SHIFT);  in rk3588_dclk_vop_set_parent()
1947 			     sel << DCLK1_VOP_SRC_SEL_SHIFT);  in rk3588_dclk_vop_set_parent()
1951 			     sel << DCLK2_VOP_SRC_SEL_SHIFT);  in rk3588_dclk_vop_set_parent()
1955 			     sel << DCLK3_VOP_SRC_SEL_SHIFT);  in rk3588_dclk_vop_set_parent()
1959 			sel = 1;  in rk3588_dclk_vop_set_parent()
1961 			sel = 2;  in rk3588_dclk_vop_set_parent()
1963 			sel = 0;  in rk3588_dclk_vop_set_parent()
1965 			     sel << DCLK0_VOP_SEL_SHIFT);  in rk3588_dclk_vop_set_parent()
1969 			sel = 1;  in rk3588_dclk_vop_set_parent()
1971 			sel = 2;  in rk3588_dclk_vop_set_parent()
1973 			sel = 0;  in rk3588_dclk_vop_set_parent()
1975 			     sel << DCLK1_VOP_SEL_SHIFT);  in rk3588_dclk_vop_set_parent()
1979 			sel = 1;  in rk3588_dclk_vop_set_parent()
1981 			sel = 2;  in rk3588_dclk_vop_set_parent()
1983 			sel = 0;  in rk3588_dclk_vop_set_parent()
1985 			     sel << DCLK2_VOP_SEL_SHIFT);  in rk3588_dclk_vop_set_parent()