295 			prate = priv->cpll_hz;  in rk3588_top_get_clk()
306 			prate = priv->cpll_hz;  in rk3588_top_get_clk()
335 		if (!(priv->cpll_hz % rate)) {  in rk3588_top_set_clk()
337 			src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3588_top_set_clk()
757 			prate = priv->cpll_hz;  in rk3588_mmc_get_clk()
769 			prate = priv->cpll_hz;  in rk3588_mmc_get_clk()
779 			prate = priv->cpll_hz;  in rk3588_mmc_get_clk()
791 			prate = priv->cpll_hz;  in rk3588_mmc_get_clk()
823 		} else if (!(priv->cpll_hz % rate)) {  in rk3588_mmc_set_clk()
825 			div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3588_mmc_set_clk()
832 		if (!(priv->cpll_hz % rate)) {  in rk3588_mmc_set_clk()
834 			div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3588_mmc_set_clk()
960 			parent = priv->cpll_hz;  in rk3588_aclk_vop_get_clk()
1014 		} else if (!(priv->cpll_hz % rate)) {  in rk3588_aclk_vop_set_clk()
1016 			div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3588_aclk_vop_set_clk()
1101 		parent = priv->cpll_hz;  in rk3588_dclk_vop_get_clk()
1181 				pll_rate = priv->cpll_hz;  in rk3588_dclk_vop_set_clk()
1229 		return DIV_TO_RATE(priv->cpll_hz, div);  in rk3588_gmac_get_clk()
1233 		return DIV_TO_RATE(priv->cpll_hz, div);  in rk3588_gmac_get_clk()
1237 		return DIV_TO_RATE(priv->cpll_hz, div);  in rk3588_gmac_get_clk()
1241 		return DIV_TO_RATE(priv->cpll_hz, div);  in rk3588_gmac_get_clk()
1253 	div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3588_gmac_set_clk()
1333 		p_rate = priv->cpll_hz;  in rk3588_uart_get_rate()
1360 	} else if (priv->cpll_hz % rate == 0) {  in rk3588_uart_set_rate()
1675 		priv->cpll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[CPLL],  in rk3588_clk_set_rate()
2032 	if (priv->cpll_hz != CPLL_HZ) {  in rk3588_clk_init()
2036 			priv->cpll_hz = CPLL_HZ;  in rk3588_clk_init()