Lines Matching refs:con
153 u32 con, sel, rate; in rk3588_center_get_clk() local
157 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
158 sel = (con & ACLK_CENTER_ROOT_SEL_MASK) >> in rk3588_center_get_clk()
170 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
171 sel = (con & ACLK_CENTER_LOW_ROOT_SEL_MASK) >> in rk3588_center_get_clk()
183 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
184 sel = (con & HCLK_CENTER_ROOT_SEL_MASK) >> in rk3588_center_get_clk()
196 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
197 sel = (con & PCLK_CENTER_ROOT_SEL_MASK) >> in rk3588_center_get_clk()
285 u32 con, sel, div, rate, prate; in rk3588_top_get_clk() local
289 con = readl(&cru->clksel_con[8]); in rk3588_top_get_clk()
290 div = (con & ACLK_TOP_ROOT_DIV_MASK) >> in rk3588_top_get_clk()
292 sel = (con & ACLK_TOP_ROOT_SRC_SEL_MASK) >> in rk3588_top_get_clk()
300 con = readl(&cru->clksel_con[8]); in rk3588_top_get_clk()
301 div = (con & ACLK_LOW_TOP_ROOT_DIV_MASK) >> in rk3588_top_get_clk()
303 sel = (con & ACLK_LOW_TOP_ROOT_SRC_SEL_MASK) >> in rk3588_top_get_clk()
311 con = readl(&cru->clksel_con[8]); in rk3588_top_get_clk()
312 sel = (con & PCLK_TOP_ROOT_SEL_MASK) >> PCLK_TOP_ROOT_SEL_SHIFT; in rk3588_top_get_clk()
382 u32 sel, con; in rk3588_i2c_get_clk() local
387 con = readl(&cru->pmuclksel_con[3]); in rk3588_i2c_get_clk()
388 sel = (con & CLK_I2C0_SEL_MASK) >> CLK_I2C0_SEL_SHIFT; in rk3588_i2c_get_clk()
391 con = readl(&cru->clksel_con[38]); in rk3588_i2c_get_clk()
392 sel = (con & CLK_I2C1_SEL_MASK) >> CLK_I2C1_SEL_SHIFT; in rk3588_i2c_get_clk()
395 con = readl(&cru->clksel_con[38]); in rk3588_i2c_get_clk()
396 sel = (con & CLK_I2C2_SEL_MASK) >> CLK_I2C2_SEL_SHIFT; in rk3588_i2c_get_clk()
399 con = readl(&cru->clksel_con[38]); in rk3588_i2c_get_clk()
400 sel = (con & CLK_I2C3_SEL_MASK) >> CLK_I2C3_SEL_SHIFT; in rk3588_i2c_get_clk()
403 con = readl(&cru->clksel_con[38]); in rk3588_i2c_get_clk()
404 sel = (con & CLK_I2C4_SEL_MASK) >> CLK_I2C4_SEL_SHIFT; in rk3588_i2c_get_clk()
407 con = readl(&cru->clksel_con[38]); in rk3588_i2c_get_clk()
408 sel = (con & CLK_I2C5_SEL_MASK) >> CLK_I2C5_SEL_SHIFT; in rk3588_i2c_get_clk()
411 con = readl(&cru->clksel_con[38]); in rk3588_i2c_get_clk()
412 sel = (con & CLK_I2C6_SEL_MASK) >> CLK_I2C6_SEL_SHIFT; in rk3588_i2c_get_clk()
415 con = readl(&cru->clksel_con[38]); in rk3588_i2c_get_clk()
416 sel = (con & CLK_I2C7_SEL_MASK) >> CLK_I2C7_SEL_SHIFT; in rk3588_i2c_get_clk()
419 con = readl(&cru->clksel_con[38]); in rk3588_i2c_get_clk()
420 sel = (con & CLK_I2C8_SEL_MASK) >> CLK_I2C8_SEL_SHIFT; in rk3588_i2c_get_clk()
491 u32 sel, con; in rk3588_spi_get_clk() local
493 con = readl(&cru->clksel_con[59]); in rk3588_spi_get_clk()
497 sel = (con & CLK_SPI0_SEL_MASK) >> CLK_SPI0_SEL_SHIFT; in rk3588_spi_get_clk()
500 sel = (con & CLK_SPI1_SEL_MASK) >> CLK_SPI1_SEL_SHIFT; in rk3588_spi_get_clk()
503 sel = (con & CLK_SPI2_SEL_MASK) >> CLK_SPI2_SEL_SHIFT; in rk3588_spi_get_clk()
506 sel = (con & CLK_SPI3_SEL_MASK) >> CLK_SPI3_SEL_SHIFT; in rk3588_spi_get_clk()
509 sel = (con & CLK_SPI4_SEL_MASK) >> CLK_SPI4_SEL_SHIFT; in rk3588_spi_get_clk()
576 u32 sel, con; in rk3588_pwm_get_clk() local
580 con = readl(&cru->clksel_con[59]); in rk3588_pwm_get_clk()
581 sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; in rk3588_pwm_get_clk()
584 con = readl(&cru->clksel_con[59]); in rk3588_pwm_get_clk()
585 sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT; in rk3588_pwm_get_clk()
588 con = readl(&cru->clksel_con[60]); in rk3588_pwm_get_clk()
589 sel = (con & CLK_PWM3_SEL_MASK) >> CLK_PWM3_SEL_SHIFT; in rk3588_pwm_get_clk()
592 con = readl(&cru->pmuclksel_con[2]); in rk3588_pwm_get_clk()
593 sel = (con & CLK_PMU1PWM_SEL_MASK) >> CLK_PMU1PWM_SEL_SHIFT; in rk3588_pwm_get_clk()
655 u32 div, sel, con, prate; in rk3588_adc_get_clk() local
659 con = readl(&cru->clksel_con[40]); in rk3588_adc_get_clk()
660 div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT; in rk3588_adc_get_clk()
661 sel = (con & CLK_SARADC_SEL_MASK) >> in rk3588_adc_get_clk()
669 con = readl(&cru->clksel_con[41]); in rk3588_adc_get_clk()
670 div = (con & CLK_TSADC_DIV_MASK) >> in rk3588_adc_get_clk()
672 sel = (con & CLK_TSADC_SEL_MASK) >> in rk3588_adc_get_clk()
746 u32 sel, con, div, prate; in rk3588_mmc_get_clk() local
750 con = readl(&cru->clksel_con[172]); in rk3588_mmc_get_clk()
751 div = (con & CCLK_SDIO_SRC_DIV_MASK) >> CCLK_SDIO_SRC_DIV_SHIFT; in rk3588_mmc_get_clk()
752 sel = (con & CCLK_SDIO_SRC_SEL_MASK) >> in rk3588_mmc_get_clk()
762 con = readl(&cru->clksel_con[77]); in rk3588_mmc_get_clk()
763 div = (con & CCLK_EMMC_DIV_MASK) >> CCLK_EMMC_DIV_SHIFT; in rk3588_mmc_get_clk()
764 sel = (con & CCLK_EMMC_SEL_MASK) >> in rk3588_mmc_get_clk()
774 con = readl(&cru->clksel_con[78]); in rk3588_mmc_get_clk()
775 div = (con & BCLK_EMMC_DIV_MASK) >> BCLK_EMMC_DIV_SHIFT; in rk3588_mmc_get_clk()
776 sel = (con & BCLK_EMMC_SEL_MASK) >> in rk3588_mmc_get_clk()
784 con = readl(&cru->clksel_con[78]); in rk3588_mmc_get_clk()
785 div = (con & SCLK_SFC_DIV_MASK) >> SCLK_SFC_DIV_SHIFT; in rk3588_mmc_get_clk()
786 sel = (con & SCLK_SFC_SEL_MASK) >> in rk3588_mmc_get_clk()
796 con = readl(&cru->clksel_con[62]); in rk3588_mmc_get_clk()
797 div = (con & DCLK_DECOM_DIV_MASK) >> DCLK_DECOM_DIV_SHIFT; in rk3588_mmc_get_clk()
798 sel = (con & DCLK_DECOM_SEL_MASK) >> in rk3588_mmc_get_clk()
900 u32 div, con, parent; in rk3588_aux16m_get_clk() local
903 con = readl(&cru->clksel_con[117]); in rk3588_aux16m_get_clk()
907 div = (con & CLK_AUX16MHZ_0_DIV_MASK) >> CLK_AUX16MHZ_0_DIV_SHIFT; in rk3588_aux16m_get_clk()
910 div = (con & CLK_AUX16MHZ_1_DIV_MASK) >> CLK_AUX16MHZ_1_DIV_SHIFT; in rk3588_aux16m_get_clk()
949 u32 div, sel, con, parent; in rk3588_aclk_vop_get_clk() local
954 con = readl(&cru->clksel_con[110]); in rk3588_aclk_vop_get_clk()
955 div = (con & ACLK_VOP_ROOT_DIV_MASK) >> ACLK_VOP_ROOT_DIV_SHIFT; in rk3588_aclk_vop_get_clk()
956 sel = (con & ACLK_VOP_ROOT_SEL_MASK) >> ACLK_VOP_ROOT_SEL_SHIFT; in rk3588_aclk_vop_get_clk()
969 con = readl(&cru->clksel_con[110]); in rk3588_aclk_vop_get_clk()
970 sel = (con & ACLK_VOP_LOW_ROOT_SEL_MASK) >> in rk3588_aclk_vop_get_clk()
981 con = readl(&cru->clksel_con[110]); in rk3588_aclk_vop_get_clk()
982 sel = (con & HCLK_VOP_ROOT_SEL_MASK) >> HCLK_VOP_ROOT_SEL_SHIFT; in rk3588_aclk_vop_get_clk()
1063 u32 div, sel, con, parent; in rk3588_dclk_vop_get_clk() local
1068 con = readl(&cru->clksel_con[111]); in rk3588_dclk_vop_get_clk()
1069 div = (con & DCLK0_VOP_SRC_DIV_MASK) >> DCLK0_VOP_SRC_DIV_SHIFT; in rk3588_dclk_vop_get_clk()
1070 sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT; in rk3588_dclk_vop_get_clk()
1074 con = readl(&cru->clksel_con[111]); in rk3588_dclk_vop_get_clk()
1075 div = (con & DCLK1_VOP_SRC_DIV_MASK) >> DCLK1_VOP_SRC_DIV_SHIFT; in rk3588_dclk_vop_get_clk()
1076 sel = (con & DCLK1_VOP_SRC_SEL_MASK) >> DCLK1_VOP_SRC_SEL_SHIFT; in rk3588_dclk_vop_get_clk()
1080 con = readl(&cru->clksel_con[112]); in rk3588_dclk_vop_get_clk()
1081 div = (con & DCLK2_VOP_SRC_DIV_MASK) >> DCLK2_VOP_SRC_DIV_SHIFT; in rk3588_dclk_vop_get_clk()
1082 sel = (con & DCLK2_VOP_SRC_SEL_MASK) >> DCLK2_VOP_SRC_SEL_SHIFT; in rk3588_dclk_vop_get_clk()
1085 con = readl(&cru->clksel_con[113]); in rk3588_dclk_vop_get_clk()
1086 div = (con & DCLK3_VOP_SRC_DIV_MASK) >> DCLK3_VOP_SRC_DIV_SHIFT; in rk3588_dclk_vop_get_clk()
1087 sel = (con & DCLK3_VOP_SRC_SEL_MASK) >> DCLK3_VOP_SRC_SEL_SHIFT; in rk3588_dclk_vop_get_clk()
1113 u32 i, conid, con, sel, div, best_div = 0, best_sel = 0; in rk3588_dclk_vop_set_clk() local
1120 con = readl(&cru->clksel_con[111]); in rk3588_dclk_vop_set_clk()
1121 sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT; in rk3588_dclk_vop_set_clk()
1129 con = readl(&cru->clksel_con[111]); in rk3588_dclk_vop_set_clk()
1130 sel = (con & DCLK1_VOP_SRC_SEL_MASK) >> DCLK1_VOP_SRC_SEL_SHIFT; in rk3588_dclk_vop_set_clk()
1138 con = readl(&cru->clksel_con[112]); in rk3588_dclk_vop_set_clk()
1139 sel = (con & DCLK2_VOP_SRC_SEL_MASK) >> DCLK2_VOP_SRC_SEL_SHIFT; in rk3588_dclk_vop_set_clk()
1146 con = readl(&cru->clksel_con[113]); in rk3588_dclk_vop_set_clk()
1147 sel = (con & DCLK3_VOP_SRC_SEL_MASK) >> DCLK3_VOP_SRC_SEL_SHIFT; in rk3588_dclk_vop_set_clk()
1223 u32 con, div; in rk3588_gmac_get_clk() local
1227 con = readl(&cru->clksel_con[81]); in rk3588_gmac_get_clk()
1228 div = (con & CLK_GMAC0_PTP_DIV_MASK) >> CLK_GMAC0_PTP_DIV_SHIFT; in rk3588_gmac_get_clk()
1231 con = readl(&cru->clksel_con[81]); in rk3588_gmac_get_clk()
1232 div = (con & CLK_GMAC1_PTP_DIV_MASK) >> CLK_GMAC1_PTP_DIV_SHIFT; in rk3588_gmac_get_clk()
1235 con = readl(&cru->clksel_con[83]); in rk3588_gmac_get_clk()
1236 div = (con & CLK_GMAC_125M_DIV_MASK) >> CLK_GMAC_125M_DIV_SHIFT; in rk3588_gmac_get_clk()
1239 con = readl(&cru->clksel_con[84]); in rk3588_gmac_get_clk()
1240 div = (con & CLK_GMAC_50M_DIV_MASK) >> CLK_GMAC_50M_DIV_SHIFT; in rk3588_gmac_get_clk()
1291 u32 reg, con, fracdiv, div, src, p_src, p_rate; in rk3588_uart_get_rate() local
1325 con = readl(&cru->clksel_con[reg + 2]); in rk3588_uart_get_rate()
1326 src = (con & CLK_UART_SEL_MASK) >> CLK_UART_SEL_SHIFT; in rk3588_uart_get_rate()
1327 con = readl(&cru->clksel_con[reg]); in rk3588_uart_get_rate()
1328 div = (con & CLK_UART_SRC_DIV_MASK) >> CLK_UART_SRC_DIV_SHIFT; in rk3588_uart_get_rate()
1329 p_src = (con & CLK_UART_SRC_SEL_MASK) >> CLK_UART_SRC_SEL_SHIFT; in rk3588_uart_get_rate()
1428 u32 con, div, src; in rk3588_pciephy_get_rate() local
1432 con = readl(&cru->clksel_con[177]); in rk3588_pciephy_get_rate()
1433 src = (con & CLK_PCIE_PHY0_REF_SEL_MASK) >> CLK_PCIE_PHY0_REF_SEL_SHIFT; in rk3588_pciephy_get_rate()
1434 con = readl(&cru->clksel_con[176]); in rk3588_pciephy_get_rate()
1435 div = (con & CLK_PCIE_PHY0_PLL_DIV_MASK) >> CLK_PCIE_PHY0_PLL_DIV_SHIFT; in rk3588_pciephy_get_rate()
1438 con = readl(&cru->clksel_con[177]); in rk3588_pciephy_get_rate()
1439 src = (con & CLK_PCIE_PHY1_REF_SEL_MASK) >> CLK_PCIE_PHY1_REF_SEL_SHIFT; in rk3588_pciephy_get_rate()
1440 con = readl(&cru->clksel_con[176]); in rk3588_pciephy_get_rate()
1441 div = (con & CLK_PCIE_PHY1_PLL_DIV_MASK) >> CLK_PCIE_PHY1_PLL_DIV_SHIFT; in rk3588_pciephy_get_rate()
1444 con = readl(&cru->clksel_con[177]); in rk3588_pciephy_get_rate()
1445 src = (con & CLK_PCIE_PHY2_REF_SEL_MASK) >> CLK_PCIE_PHY2_REF_SEL_SHIFT; in rk3588_pciephy_get_rate()
1446 div = (con & CLK_PCIE_PHY2_PLL_DIV_MASK) >> CLK_PCIE_PHY2_PLL_DIV_SHIFT; in rk3588_pciephy_get_rate()